The practical engineer-fine-tuning memory macros using variable internal delays

Abstract

Embedded memory blocks are extremely common in application-specific IC (ASIC) chips. In this era of design reuse, it is critical that these memory macros, as they are also called, should be as versatile as possible. Their performance should be optimal, with adequate sense amplifier signal over the full manufacturing process range of the chip. Fortunately, several simple techniques exist for adapting memory macros to different applications running at different speeds. The key is to design in delays that are variable and/or programmable. The approach is also helpful in debugging initial hardware where a memory macro is refusing to function because its timing is too fast and there is insufficient internal delay for proper circuit operation. The techniques can also eliminate the process of redesigning and refabricating the initial hardware just to characterize it. A memory macro is made to function by internal pulses, generated in the correct number, sequence and relationship by the internal timing chain. The timing chain can be interlocked with the circuitry being driven by the addition to the macro of a set of circuits mimicking the operation of the primary circuitry.