The Parasitic-Aware Design and Optimization of CMOS Distributed Amplifier Using Multi Objective Genetic Algorithm

Abstract

In this paper a fully integrated CMOS Distributed Amplifier is presented. This DA can be used for broadband optical and wireless communication applications. A four stage cascode DA is designed and optimized. A critical problem in CMOS RFIC design is the parasitic elements of transistors and inductors and this problem makes handed design methodology complex. Here a CAD tool underpins the parasitic-aware methodology used to optimize the design including all on-chip active and passive devices and bias voltages. Optimization is a new method based on Distributed Pareto-based Multi-Objective Genetic Algorithm that is introduced for RFIC design optimization. The optimization system is parasitic-aware and simulation-based. Through a link between HSPICE and MATLAB, all transistor sizes, bias voltages and number of turns and diameter of inductors are proposed by CAD and then circuit, with these values are simulated by Hspice-RF. The output parameters, such as gain, bandwidth, S11, S22 and power are extracted from output file and the area of chip is calculated separately. This output parameters are used as cost functions for creating next generation. This algorithm is implemented by Matlab and simulated by Hspice-RF with TSMC 0.18u CMOS technology.