The MPEG-4 based energy efficient application traffic modelling and synthesis for network-on-chip architecture

Abstract

A technological demand made the integration of multi core chips into a single chip which leads to the advancement of processing elements and memory units. But this leads to communication between cores more challenging. On the downside, simulation with real traffic becomes inflexible and time-consuming. This paper analyzes a novel method for generation of the self-similar process exhibited by the bursty HVEC MPEG-4 video applications for the on-chip architecture with the algorithm running cost at most O(nlogn). Statistical properties of the relevant generated traces from the video clips show the existence of the self-similarity in the traffic of high MPEG-4 video. The multicore architecture helps us in highlighting the inference of the findings on the size of memory (buffer) and present required quantitative analysis for various video streams running on on-chip architecture. We have generated traces from the statistical properties of videos using the Circular Embedding Technique (CIET) resemblance with the bursty nature. Parameters are analyzed under different traffics and loads which results in the reduction of power and latency. Our methodology is to figure the buffer loss probability for the fixed-sized buffer framework utilizing Maximum Variance Asymptotic (MVA) approximations open new bearings and information on research with better ramifications on comparable crucial issues for mixed media applications for on-chip network structure.