The Kinetics of Removal of Defects in a-Si:H TFTs Made with PECVD Oxide Gate Insulator Material

Abstract

ABSTRACTAMorphous silicon thin film transistors may be manufactured using a variety of gate insulator Materials. The sign and magnitude of the fixed charge, Qf, in the gate insulator material determines the as-deposited density of states in the a-Si:H as predicted by the defect pool Model [1]. For the case of PECVD nitride Qf is positive giving rise to a defect peak in the lower part of the bandgap. In thermal oxide, which has small negative Qf the states are in the upper part of the bandgap. Using the technique of low temperature bias stress or high temperature bias anneal it is possible to create further defects in the bandgap on top of those already present, facilitating the study of upper (Dh) and lower (De) gap states. In a previous work we studied the removal kinetics of such defects using TSDR (Thermally Stimulated Defect Removal) in both PECVD nitride and thermal oxide devices [2]. Here we repeat the experiments on thin film transistors made with PECVD helium diluted oxide as the gate insulator Material. PECVD helium diluted oxide is interesting as its Qf May be varied during Manufacture. Thus TFTs with characteristics similar to either thermal oxide or PECVD nitride can be obtained.