Abstract
The electrical characteristics of top select gate transistor (TSG) has been investigated in vertical channel three dimensional NAND flash memory. TSG shows wider initial Vth distribution as compared with memory cells, and even worse after erase. By experimental analysis and TCAD simulation, a physical model based on grain boundary (GB) interface traps is proposed to explain the mechanism. Grain boundary traps in offset region between bit line contact and TSG can induce a higher local potential barrier in channel, which results in higher TSG initial Vth. Besides, random GB position within offset region, leads to worse variation of TSG initial Vth. Furthermore, the local potential barrier in offset region of TSG cannot be reduced by erase operation, leading to worse Vth distribution after erase. According to proposed model, two methods with optimization of offset doping energy and poly-Si GB trap passivation condition are proposed to achieve tight distribution and improved erase uniformity.
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