Abstract
As device scaling becomes increasingly difficult, 3D integration with through silicon via (TSV) has emerged as a viable solution for addressing the requisite bandwidth and power efficiency challenges. However, mechanical stresses induced by the TSVs must be controlled in the 3D flow in order to preserve the electrical integrity of front-end devices. Since copper filling material of the TSV could causes stresses on silicon near the TSV, the impact of TSV proximity on CMOS must be evaluated at various operation temperatures. In this paper, Cu-filled TSVs were fabricated in “via middle” process. The TSVs-induced mechanical stresses causing carrier mobility change that result in drive current (I on ) variation. In order to obtain robust design rules (i.e. keep-out zone) and spice model for TSV applications, electrical characteristics of CMOS devices were investigated in terms of distance between TSV and CMOS device in this work.
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