The Effects of Valence Band Offset on Threshold Voltage Shift in a-InGaZnO TFTs Under Negative Bias Illumination Stress

Abstract

In this paper, we propose a novel mechanism for the $\text{V}_{{\text {th}}}$ shift of amorphous-indium gallium zinc oxide (a-IGZO) thin film transistors under negative bias illumination stress (NBIS). Three kinds of IGZO TFTs with different gate dielectrics and valence band offsets (VBO) were used in this experiment. Gate dielectric materials used were Al2O3, HfO2 and SiO2. Initial parameters, VBO, and state density (DOS) for each TFT were extracted. After NBIS, the $\text{V}_{\text {th}}$ shift was greatest at −3.82 V using a TFT with an HfO2 gate dielectric. VBO was the lowest at 0.38 eV using a TFT with an HfO2 gate dielectric. The smaller the VBO, the larger the generated $\text{V}_{\text {th}}$ shift. DOS measurements confirmed the interfacial properties between the gate dielectric and IGZO, and the highest DOS resulted from the interface between Al2O3 and IGZO. Through the experimental results, the correlation between VBO and $\Delta \text{V}_{{\text {th}}}$ after NBIS was investigated. We found that the main cause of $\text{V}_{{\text {th}}}$ shift in NBIS is injection of photoinduced hole carriers that cross the VBO by tunneling from IGZO channel to gate oxide.