The effect of RTP pretreatment on slip-lines of argon annealed silicon wafer

Abstract

In this research, Rapid Thermal Process (RTP) pretreatment technology was used to study the slip-lines of 12-inch light boron-doped silicon wafer with Oxidation Induced Stacking Fault (OISF) ring which will be used for argon annealing. X-ray Diffraction Topography (XRT) test results were shown that Rapid Thermal Processing (RTP) pretreatment below 1250 °C would lead to the deterioration of slip-lines during argon annealing, and that RTP pretreatment no less than 1250 °C would eliminate slip-lines. Bulk Micro Defects (BMD) tests show that RTP pretreatment can deteriorate or eliminate slip-lines resulted from argon annealing. When the RTP pretreatment temperature is lower than 1250 °C, the native BMD nuclei smaller than the critical size will eliminate. During argon annealing, the growth of the residual native BMD nuclei formed during ingot pulling process is the dominant process, while formation and growth of new nuclei are less, resulting in both the reduction of BMD density and broadening distribution of BMD size. Then we see the slip-lines of silicon wafer will become worse due to the increase of thermal stress in the silicon wafer. However, when the RTP pretreatment temperature is no less than 1250 °C, the native BMD nuclei will be completely eliminated and a vacancy enriched layer will be formed in the silicon wafer. During argon annealing, vacancies promote the uniform nucleation of BMD, the density of BMD increases and the size distribution becomes narrow, and the thermal stress in the silicon wafer is relatively lower, thus the slip-lines are eliminated.