Abstract
This paper is concerned with digital sub-systems comprising bistable flip-flops connected to a common source of clock-pulses. This configuration, of which the feedback shift register is the most important special case, is useful for the generation of periodic binary codes and sequences. It is assumed that the building-blocks for these circuits are integrated J-K flip-flops and NAND gates, and design techniques appropriate for this situation are described.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
