Abstract
Benchmark one of the DARPA HPCS discrete mathematics suite for high productivity computing involves multiple precision arithmetic. The benchmark computes the product of two given N times N matrices whose entries are multiple precision integers, with the product being taken modulo another multiple precision integer M. The authors describe algorithms and methodologies for three implementations of this benchmark on SRC computers' SRC-6 reconfigurable platform and present performance results. The use of pipeline parallelism from inner loops, parallel code sections, and the two FPGA chips on the SRC hardware can speed up performance by as much as 20times compared to a software only implementation
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
