The Current Status and the Future Prospects of Surface Passivation in 4H-SiC Transistors

Abstract

The degraded performance of 4H-SiC transistors due to a high density of the SiC/SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> interface states (D <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">IT</sub> ) (~10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">12</sup> -10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">13</sup> eV <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-1</sup> cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-2</sup> ) has gained increasing attention in recent years. A significant amount of research is being done to improve the fabrication process of 4H-SiC devices to achieve a good quality interface, thereby reducing D <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">IT</sub> to an acceptable value. This paper analyzes the current passivation schemes and their effectiveness in lowering D <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">IT</sub> and potentially improving the performance of 4H-SiC metal-oxide-semiconductor-based devices and bipolar junction transistors. This paper also discusses the processes that affect the interface quality, such as surface preparation, oxidation methods, postoxidation annealing conditions, and other processes, such as the use of alternative dielectrics. The possibility of substantially improving the interface quality by combining some of these processes is also examined.