The Calculation and Anticipation Unit for Floating-Point Addition

Abstract

Most recent microprocessors present multiple special functional units to optimize their performance. In this paper, a new functional unit called the calculation and anticipation (C&A) unit is presented for the IEEE 754 standard floating-point adder (FPA) that is the most important and frequently used calculation part for both modern CPUs and GPUs. C&A unit parallelize rounding step and readjustment step, which are known as the time-consuming steps for floating-point addition with significand addition. Therefore it reduces FPA critical path delay enormously, and even more decreases a little FPA area occupation. The synthesis results show that the double-precision FPA with C&A unit takes about 17.17% improvement in the critical path delay, while saves about 8.32% area than the conventional one. It takes 5.90% advantage in area and 19.58% improvement in the worst case delay than the double-precision FPA from the Open Core module "fpu_double" (rev 14 2010-02-13) synthesized in the same 0.13-μm CMOS bulk. Furthermore, comparing with the two-path double-precision FPA synthesized using LSI Logic's gflxp 0.11-μm CMOS library, it takes about 4.30% advantage in the critical path delay, and saves almost one-third area in the number of the individual cells.