Abstract
The NORA-CMOS (no-race complementary metal-oxide-silicon) serial-parallel multiplier presented here is testable. Error detection is achieved at two levels: online functional testing and offline structural testing. Functional testing uses low-cost residue codes to detect errors at the overall level. Modulus is adopted as the check base. For structural testing, a NORA CMOS circuit error detection technique proposed based on the structure, properties, and operations of NORA CMOS is used. The proposed technique can detect output stuck-at, stuck-open, and stuck-on faults. Such a two-level testing strategy reduces test time and chip area overhead, identifies faulty locations, and has the ability to detect both transient and permanent faults.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
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