Testing high-frequency and low-power designs: Do the standard rules and tools apply?

Abstract

The fast growing mobile market has led to a demand for low power ICs, in order to extend battery life and keep a phone from literally burning a hole in the user's pocket. The microprocessor and high-end System on a Chip field both have a demand for faster ICs. But this is not enough. Mobile devices want to be faster, and high-end devices want to be cooler, if possible. Designers have to be able to tradeoff these conflicting goals to produce products fast enough and cool enough (in both senses of that word) for the marketplace. DFT and test engineers have to deal with this new environment. They have to be able to determine if a particular part hits its speed goals. They have to be able to handle the problems arising from large amounts of switching. For low power parts they have to make sure that scan and BIST do not draw more power than the part can handle, and work around circuitry that turns off parts of the design not in use. Test EDA suppliers have to figure out ways of making their tools work for both high speed and low power designs, and how to help their customers make these nearly impossible tradeoffs. This panel explores these problems and their impact on EDA tools. Three test experts from the design world will answer questions on how they deal with the problems of low power and high speed designs posed by the moderator. Then two panelists from the test EDA sector will suggest how their tools can help — or admit that their tools need more work in that area. Then the discussion will be opened to the audience to allow them to give their solutions to these problems or to pose still tougher problems for us to solve.