Test Pattern Generation of VLSI Circuits Using Hopfield Neural Networks

Abstract

A new test pattern generation method for the stuck-at faults in VLSI circuits is presented in this paper, the method uses Hopfield neural networks and chaotic simulated annealing. The Hopfield neural network corresponding to a digital circuit is built, the test patterns of faults in digital circuits are produced by computing the optima of the energy function. A chaotic simulated annealing algorithm is designed, which combines the features of chaotic systems and conventional simulated annealing, it is able to take the advantages of the stochastic properties and global search ability of chaotic system. The algorithm is used to compute the optima of the energy function of neural networks in order to produce the test patterns of faults. Experimental results show that the test pattern generation method proposed in this paper can produce the test patterns in short time for both single stuck-at faults and multiple stuck-at faults in digital circuits.