Termal packaging limit for hybrid superconductor-semiconductor electronic circuits.

Abstract

The discovery of superconductivity above 90K opens up the possibility of powerful hybrid electronic circuits. Superconductive electronic devices exhibit effects of temperature not present in semiconductors. Heat dissipations in transistors cause temperature fields in hybrid chips that affect the performance of the superconductive element, the Josephson junctions. The minimum distance between semiconductor and superconductor elements results in a thermal packaging limit for hybrid chips. This work presents a novel methodology to determine this limit, based on the basic thermal phenomena in superconductive elements. An approximate one-dimensional thermal analysis of a generic hybrid chip design determines the temperature field and the minimum distance.