Template-based AADL automatic code generation

Embedded real-time systems are widely used in avionics, spacecraft, automotive automation, robotics, mobile communications and other fields. In order to detect errors in the development of embedded real-time systems, the development method of model-driven is widely applied. Model-driven finds the potential problems as early as possible by modeling and validating the system at the early stage of design. In the implementation phase of the coding, the code is automatically generated from the validated model to improve the automation of the system development, reduce R & D costs and the possibility of errors in coding process. The research of code generation technology based on architecture analysis and design language (AADL) is an important research content of embedded software development. AADL is a language that models the graphical representation of modeling elements and models in textual form. The C language can compile and process low-level memory in a simple way, generate a small number of machine codes, and run without any support from running environment. Aiming at the characteristics of the above two languages, so we design an automatic code generation tool that automatically converts AADL model into C codes.

Wind energy has the advantages of wide distribution, renewable, and non-polluting, so it is receiving more and more attention from more and more countries. As more and more wind power systems are integrated into the grid, it has an impact on the stability of the grid. To keep the power system stable, there is an urgent need for a grid simulator that can simulate various behaviors of the grid and test the reliability of the wind turbine before grid integration. Inverters, especially multilevel inverters, as the core part of the grid simulator, have been widely studied by scholars in recent years. However, compared to conventional inverters, multilevel inverters are characterized by high code development effort, great difficulty, and a long development period. In this paper, we adopt an automatic DSP code generation method with MATLAB hardware support package and give a complete system design method and development flow based on MATLAB and TMSF28335 automatic code generation. Finally, we take the closed-loop three-level MMC inverter as an example, propose an equalization algorithm suitable for automatic code generation for the capacitor-voltage balancing part, and verify the feasibility of the DSP automatic code generation in a multilevel inverter development. The feasibility of DSP automatic code generation in the development of a multilevel inverter is verified. The experimental results show that the proposed equalization algorithm with variable reference coefficient and DSP automatic code generation method can be used in the development of a multilevel inverter, which can improve development efficiency and reduce development costs.

For Safety Critical CPS applications, Architecture Analysis and Design Language (AADL) can provide a framework for formally modeling end-to-end Cyber Physical Systems (CPS). Such a model includes hardware platform model, software architecture model, the real-time bounds on software and hardware components. An AADL model of the system allows early formal analysis of real-time schedulability, end-to-end performance, power, memory requirements and correctness. Multiple tool support for AADL modeling and analysis exists, including software code generator, which glues together software components declared in the software architecture model. Ocarina is one such tool for software generation but it requires that the modeler provides the subprogram code in C/C++ or Ada. For correct-by-construction code synthesis, it is ideal to eliminate manually written code, and instead of using Ocarina as a glue code generator, using it for complete code synthesis from formal models. Support for Esterel and Lustre based specification of subprograms already have been attempted, but they usually specify specific subprogram elements, and the specific code generators are invoked to synthesis C/C++ code and then Ocarina glues them together based on the architectural constraints specified in the AADL model. This means that in a multi-threaded or multi-process software architecture, we still have to maneuver to get correct synchronization code. Moreover, if the granularity of code synthesis is at the function or subprogram level, we cannot gain much towards the goal of correct-by-construction synthesis and we believe that taking advantage of polychronous modeling and code synthesis would be ideal to achieve that goal. In this work, we show how to extend the Ocarina code generator to work with our Polychronous modeling and code synthesis solution to obtain multi-threaded code, improving the code-synthesis granularity from subprograms to processes while guaranteeing the implementation correctness. Moreover, a real-time extension of our polychronous code synthesis can provide the opportunity to enhance the real-time schedulability analysis of AADL. In this paper, we will outline the problem of AADL based model-driven implementation of CPS systems, describe the state-of-art code generation through Ocarina, point out why the extensions we propose are needed, and finally describe our code synthesis extension for multi-threaded code synthesis in our AADL modeling, analysis and code synthesis tool APECS which extends OSATE and Ocarina tools for AADL.

A promising trend in software development is the increasing adoption of model-driven design. In this approach, a developer first constructs an abstract model of the required program behavior in a language, such as Statecharts or Stateflow, and then uses a code generator to automatically transform the model into an executable program. This approach has many advantages---typically, a model is not only more concise than code and hence more understandable, it is also more amenable to mechanized analysis. Moreover, automatic generation of code from a model usually produces code with fewer errors than hand-crafted code.One serious problem, however, is that a code generator may produce inefficient code. To address this problem, this paper describes a method for generating efficient code from SCR (Software Cost Reduction) specifications. While the SCR tabular notation and tools have been used successfully to specify, simulate, and verify numerous embedded systems, until now SCR has lacked an automated method for generating optimized code. This paper describes an efficient method for automatic code generation from SCR specifications, together with an implementation and an experimental evaluation. The method first synthesizes an execution-flow graph from the specification, then applies three optimizations to the graph, namely, input slicing, simplification, and output slicing, and then automatically generates code from the optimized graph. Experiments on seven benchmarks demonstrate that the method produces significant performance improvements in code generated from large specifications. Moreover, code generation is relatively fast, and the code produced is relatively compact.

A promising trend in software development is the increasing adoption of model-driven design. In this approach, a developer first constructs an abstract model of the required program behavior in a language, such as Statecharts or Stateflow, and then uses a code generator to automatically transform the model into an executable program. This approach has many advantages---typically, a model is not only more concise than code and hence more understandable, it is also more amenable to mechanized analysis. Moreover, automatic generation of code from a model usually produces code with fewer errors than hand-crafted code.One serious problem, however, is that a code generator may produce inefficient code. To address this problem, this paper describes a method for generating efficient code from SCR (Software Cost Reduction) specifications. While the SCR tabular notation and tools have been used successfully to specify, simulate, and verify numerous embedded systems, until now SCR has lacked an automated method for generating optimized code. This paper describes an efficient method for automatic code generation from SCR specifications, together with an implementation and an experimental evaluation. The method first synthesizes an execution-flow graph from the specification, then applies three optimizations to the graph, namely, input slicing, simplification, and output slicing, and then automatically generates code from the optimized graph. Experiments on seven benchmarks demonstrate that the method produces significant performance improvements in code generated from large specifications. Moreover, code generation is relatively fast, and the code produced is relatively compact.

Development of modern systems has reached a scale and complexity that makes it unrealistic to realize the function of systems in traditional way of software development. The way of development based on model driven architecture has improved the activities of software development radically, and has gradually become the mainstream way of development. The architecture analysis and design language (AADL), put forward by some organizations such as SAE and so on, is a kind of modeling language based on the method of MDA, which modeled in architecture level with the unit of components. After system modeling, how to generate codes by AADL model automatically is a problem cried for solution. This paper designs an automatic code generator based on AADL model, put forward the mapping rule from the element of AADL model to that of C language, and conducts validation test with the combination of DELTA OS, a embedded real-time operating system with independent intellectual property rights, and LAMDA PRO, a integration development platform, accordingly proves the validity of generating C program automatically from AADL model.

Model-based design is an effective means for rapid development of embedded software, and automatic code generation is an important technology for model-based development. Combining the automatic code generation method of Matlab and STM32 with the operation and control of the autonomous underwater robot makes the design of the system more convenient. Use tools such as the Simulink library STM32 MAT/Target and STM32 CubeMX of the STM32 microcontroller to realize the automatic generation of readable and portable C code project files. At the same time, based on the design of the model, the control code of the autonomous underwater robot(AUV) is automatically generated, and the control code is added to the automatically generated C code project file. With Matlab/Simulink as the basic software platform, the motion controller of AUV is mounted on the STM32F407, and a real-time simulation system for the closed-loop control of AUV manipulation motion is constructed. The results of the semiphysical real-time simulation test show that the AUV motion controller has good heading depth control performance, realizes the manipulation and control of AUV, and verifies the practicability of the automatically generated code.

Existing Data Code Generation for CBTC system is composed of a manual switching, a automatic code generation method is proposed in this paper. The method is based on the writing diagram produced for a CBTC system, and uses the hierarchical processing architecture for all data and the sequential heuristics procedure to realize the code generation, At last, we try to apply the approach to the code part from Beijing Yi Zhuang Metro Line from CI to ZC which complete the interface code automatic generation after seven steps. Finally, we design a program by C to prove its feasibility.

The numerous interfaces of spacecraft OBDH software and frequent changes in requirements, resulting in the low efficiency and reliability of the manual coding of OBDH software. An automatic code generation method based on electronic data sheet (EDS) is proposed. The EDS system is introduced, and the output of the EDS system can be used to generate OBDH software code automatically, which improves the efficiency of software development. An structure of OBDH software is designed, which separates the logical code from the parameter code. Due to the EDS system data source is unique, and software code is automatically generated by tools, which avoids the mistakes of coding manually and promotes the reliability of OBDH software and even the reliability of spacecraft is improved.

The complexity of embedded systems design is continuously augmented, due to the increasing quantity of components and distinct functionalities incorporated into a single system. To deal with this situation, abstraction level of projects is incessantly raised. In addition, techniques to accelerate the code production process have appeared. In this context, the automatic code generation is an interesting technique for the embedded systems project. This work presents an automatic VHDL code generation method based on the OpenMP parallel programming specification. In order to synthesize C code for loops into hardware, the authors applied the directives of OpenMP, which specifies portable implementations of shared memory parallel programs. A case study focused on the use of embedded systems for the DCT algorithm is presented in this paper to demonstrate the feasibility of the proposed approach.

The increasing reliance on automatic code generation integrated with Generative AI technology has raised new challenges for cybersecurity defense against code injection, insecure code templates, and adversarial manipulation of an AI model. These risks make developing advanced frameworks imperative to ensure secure, reliable, and privacy-preserving code generation processes. The paper presents a novel Hybrid Artificial Neural Network (ANN)-Interpretive Structural Modeling (ISM) Framework to alleviate the cybersecurity risks associated with the automatic code generation using Generative AI. The proposed framework integrates the predictive capability of ANN and structured analysis of ISM for the identification, evaluation, and treatment of common vulnerabilities and risks in automatic code generation. We first conduct a multivocal literature review (MLR) to identify cybersecurity risks and generative AI practices for addressing these risks in automatic code generation. Then we conduct a questionnaire survey to identify and validate the identified risks and practices. An expert panel review was then assigned for the process of ANN-ISM. The ANN model can predict potential security risks by learning from historical data and code generation patterns. ISM is used to (1) structure and visualize (2) relations between identified risks and mitigation approaches and (3) offer a combined, multi-layered risk management methodology. We then perform an in-depth examination of the framework with a case study of an AI-based code generation company. We further determine its practicality and usefulness in real-world settings. The case study results show that the framework efficiently handles the primary cybersecurity challenges, such as injection attacks, code quality, backdoors, and lack of input validation. The analysis characterizes the maturity of several mitigation practices and areas for improvement for security integration with automatic code generation functionality. Advanced risk mitigation is enabled in the framework across multiple process areas, where techniques such as static code analysis, automated penetration testing, and adversarial training hold much promise. The Hybrid ANN-ISM Mechanism is a stable and flexible solution for cybersecurity risk reduction in automatic code generation environments. The coupling of ANN and ISM, in terms of predictive analysis and structured risk management, respectively, contributes effectively towards the security of AI-based code generation tools. More research is required to improve the scalability, privacy preserving, and dynamic integration of the framework with cybersecurity threat intelligence.

Automatic code generation is a standard method in software engineering since it improves the code consistency and reduces the overall development time. In this context, this paper presents a design flow for automatic VHDL code generation of mppSoC (massively parallel processing System-on-Chip) configuration. Indeed, depending on the application requirements, a framework of Netbeans Platform Software Tool named MppSoCGEN was developed in order to accelerate the design process of complex mppSoC. Starting from an architecture parameters design, VHDL code will be automatically generated using parsing method. Configuration rules are proposed to have a correct and valid VHDL syntax configuration. Finally, an automatic generation of Processor Elements and network topologies models of mppSoC architecture will be done for Stratix II device family. Our framework improves its flexibility on Netbeans 5.5 version and centrino duo Core 2GHz with 22 Kbytes and 3 seconds average runtime. Experimental results for reduction algorithm validate our MppSoCGEN design flow and demonstrate the efficiency of generated architectures.

FMECA (Failure Modes, Effects and Criticality Analysis) is an effective systematic process to evaluate software safety. In this paper, the safety model of embedded systems is built by integrating the AADL (Architecture Analysis and Design Language) model with extension of Error Model Annex, and the FMECA is adopted as a qualitative safety analysis for AADL (Architecture Analysis and Design Language) model of embedded system based on AADL safety model. The traditional FMECA method is improved to be suitable for AADL model evaluation, and some safety properties are added into AADL error model annex in order to fill in FMECA check list automatically at AADL modeling design phase. On using the OVP (Over Voltage Protection) system, a case study is demonstrated the feasibility of modified FMECA for AADL model.

To analyze the various non-functional properties of the AADL (Architecture Analysis and Design Language) model, many model transformation processes transform different AADL elements to different Petri nets. Unifying these transformation processes into a single process can greatly facilitate architects analyzing multiple properties simultaneously. The difficulty is that the specific elements in specific Petri nets lead to different transformation rules of different transformation processes. Some studies transformed AADL model to Petri Net Markup Language (PNML), the interexchange format of different kinds of Petri nets, to realize the unification, but only supported the transformation of part of the AADL architecture model elements. This paper proposes a framework for analysis of non-functional properties of AADL model, improving the unification work by supporting more AADL elements transforming to PNML. We establish the transformation rules mapping elements in AADL error model and behavior model to PNML. In addition, we transform AADL properties to tool specific information in PNML to generate specific Petri nets.

At present, there are many researches on automatic code generation methods based on machine learning. However, there is no analysis on automatic code generation tools based on machine learning. According to the role of existing code generation tools based on machine learning in practical development, this paper proposes the content and the method of analysis of automatic code generation tools based on machine learning. Based on the presented method, the corresponding analysis plug-ins API4ACGT are implemented. Finally, three existing automatic code generation tools based on machine learning are used to generate specific codes in two programming environments. The experimental results show that the proposed method and analysis plug-ins API4ACGT are effective.