Temperature Insensitive Clock Buffer and Its Application on Clock Tree

Abstract

High power density and uneven power density distribution caused large thermal space gradient on VLSI. Since CMOS gate delay is highly relevant to temperature, the thermal gradient could impact the performance of IC by increasing clock tree skew on chip. To maintain circuit performance, we utilize thermal behavior discrepancy between P and N type CMOS transistors to reduce clock skew under this circumstance. First, this paper proposes a kind of temperature insensitive clock buffer with cross-coupled structure. Second, a clock tree is then built based on proposed buffer to reduce clock skew induced by thermal gradient. Unlike traditional methods, the proposed circuit can work under normal supply voltage and no special voltage converter is needed.