Temperature Effects on Electrical Response of FinFET Transistors in the Static Regime

Abstract

The aim of this work is to develop an electrothermal model capable of predicting the FinFET operating temperature in different drain and gate biases with different gate lengths. A new effective electron mobility that depends on mobility degradation due to phonon scattering, surface roughness, and to Colombian interaction is used to enhance the drift-diffusion (D-D) model. To better investigate the electrical characteristics, heat conduction equation is coupled with the D-D model. To achieve high evidence to the proposed model, the simulation of ID-VG and ID-VD is compared with experimental data and Monte Carlo (MC) simulation, and a good concordance is observed. The output characteristics degradation due to device temperature is analyzed. We demonstrated that a drain current of 1 mA/_m is obtained when the operating temperature is around 360 K for a 20-nm FinFET. The effect of FinFET biases on power dissipation and device temperature along the channel region and in the drain side channel region interface is investigated for 10-and 20-nm FinFET gate lengths. We found that: 1) the power dissipation is four times greater when the gate length decreases from 20 to 10 nm and 2) the critical temperature, which is responsible to vanish the drain current, is from 380 to 460 K for Lg <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$=$</tex-math> </inline-formula> 20 and 10 nm, respectively. This work addresses a key reliability constraint for CMOS-based FinFET circuit designers while designing tuned gate and drain biases circuit.