Abstract
In this paper, an analytical model has been proposed to evaluate the effect of temperature on gate-induced drain leakages (GIDL) in a dual-metal nanowire field-effect transistor. Surface potential, electric field <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${E} _{z}$ </tex-math></inline-formula> , and GIDL current <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${I}_{\text {GIDL}}$ </tex-math></inline-formula> have been formulated and analyzed by solving 2-D Poisson’s equation with appropriate boundary conditions. The calefaction effect has also been inspected for potential and hole concentration contour plot along with in depth analysis of conduction band energy and valence band energy. Drain-induced barrier lowering and electron velocity have also been examined. Furthermore, the effect of temperature on <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${g} _{m}$ </tex-math></inline-formula> , <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${g} _{d}$ </tex-math></inline-formula> , noise figure, and noise conductance has also been examined.
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