Technology and design architectures and process innovations for 7 and 5nm BEOL interconnects

Abstract

For a semiconductor technology node, the BEOL definition must support minimal parasitic impact to technology, sufficient reliability, required dimensional scaling from previous nodes for standard cell and custom logic requirements, and high yielding/low cost integration schemes. This talk will discuss the key BEOL elements and innovations in these areas for the 7nm nodes and beyond. The individual elements are often in conflict with each other, but must be considered in unison to determine the overall best definition. For the 7nm node and future nodes, the BEOL resistance and capacitance is a significant portion of the parasitic degradation of overall technology performance. The BEOL resistance does not scale, due to exponential increases in Cu resistivity with technology scaling and Cu diffusion barrier thicknesses which approach their fundamental limits. Challenges for scaling for BEOL capacitance include integration issues which tend to drive the effective dielectric constant higher than the modeled values. BEOL Reliability is challenged by both operation voltage requirements - which are not scaling as fast as pitch scaling - and by non-scaling current requirements which strain electromigration performance. Dimensional scaling historically has been to a certain pitch scale factor from a previous node typically, 0.7 to 0.8. This smaller scaling factor provides a technology density benefit, but causes acute resistance parasitic issues. In addition, scaling to smaller dimensions highlights integration yield/cost issues. In the 7 and 5 nm nodes, the possible patterning approaches are a combination of double or quadruple exposed optical lithography or single or double exposed EUV. Aggressive scaling of pitch pushes patterning further away from known, demonstrated manufacturing solutions and adds risk to overall integration yield and cost targets.