System on chip generation for multi-sensor and sensor fusion applications

Abstract

The amount of smart devices in our daily lives has dramatically increased. Many of these devices include sensors to capture their environment and communicate with other devices, forming the internet of things (IoT). A similar process of increasing intercommunication and digitization can be seen in industry where this development is called Industry 4.0. In this new era there is a strong demand for new computing architectures that fulfill the tight energy constraints as well as deliver enough on-chip processing performance. Off-the-shelf microcontrollers do not suffice both requirements as the power to performance ratio is too high. One solution are system on chip (SoC) architectures with domain specific application specific processors (ASIP). However, this new and competitive market requires a strongly reduced time to market. Thus, it is necessary to speed up the design process and deliver enough flexibility to adapt to new applications. Therefore, we propose a new SoC generation framework, which is based on an ASIP architecture. Architectural templates can be combined with existing intellectual property (IP) components, high-level synthesis (HLS) or hardware description language (HDL) code to speed up the design process. Both field programmable gate array (FPGA) and application specific integrated circuit (ASIC) back ends are supported. The architecture targets primarily multi-sensor and sensor fusion applications. A customizable MIPS processor with an adaptable compiler toolchain ensures interoperability in standard networks. The capabilities of our SoC architecture is demonstrated on two real world problems, including a performance demanding power quality monitoring application and a low-power swimming exercise tracking applications. Results show that the application constraints can be easily fulfilled while increasing speed and flexibility in the design process.