Synthesis of Sequential Circuits by Redundancy Removal and Retiming

Abstract

In this paper we propose a method for synthesizing sequential circuits to reduce the number of gates and flip-flops by removing both combinationally and sequentially redundant faults. In order to remove sequentially redundant faults these faults are converted into combinationally redundant faults by using retiming techniques and the combinationally redundant faults can be removed by using a test pattern generation method for combinational circuits. To simplify a given circuit retiming is utilized for two purposes in this method. One is to find sequentially redundant faults and another is to reduce the number of flip-flops and gates. Before and after each retiming the combinationally redundant faults are removed. Experimental results for ISCAS ‘89 benchmark circuits show that this method can remove many of sequentially redundant faults and can reduce a large number of gates and flip-flops.