Synthesis of hazard-free control circuits from asynchronous finite state machines specifications

Abstract

We discuss a special class of state machine specifications called Asynchronous Finite State Machines (AFSM) which allows the specification and synthesis of hazard-free control circuits under the unbounded delay model. AFSM are useful for the specification of sequential behavior involving choices. In contrast, models such Signal Transition Graphs (STGs) are more amenable to the specification of deterministic concurrent behavior. AFSM specifications are transformed into STGs and then to State Graphs (SGs). At the SG level of representation, hazards can be identified as a type of violations of the Complete State Coding (CSC) property. Algorithms for obtaining SGs from AFSMs, and conditions for hazard-free implementation of SG derived from AFSM are discussed. A hazard-free synthesis technique from SG is described. A CAD prototype called CLASS (Cirrus Logic Asynchronous Synthesis System) has been built and used to successfully synthesize and verify the state machine benchmark from HP Laboroatories [1] and various other real applications.