Symbol detection in a MIMO wireless communication system using a FeFET-coupled CMOS ring oscillator array

Independent component analysis for multiple-input multiple-output wireless communication systems

Silicon MOSFETs for ULSI: Scaling CMOS to Nanoscale

Ferroelectric field effect transistor (FeFET) is a promising memory cell for space application. The FeFET can achieve non-destructive reading, and has the advantages of simple structure and high integration. Ferroelectric thin film’s size effect, retention performance and radiation resistance of ferroelectric thin films directly determine the performances of FeFET devices. The HfO<sub>2</sub> is widely used as a dielectric in complementary metal oxide semiconductor (CMOS) device and can solve the common integration problems for ferroelectric materials due to its CMOS compatibility. When the HfO<sub>2</sub>-based FeFETs are applied to aerospace electronics, the effects of various radiation particles need to be considered. The HfO<sub>2</sub>-based FeFET memory is still in the experimental stage, and there are no products of HfO<sub>2</sub>-based FeFET chips available from the market, so it is difficult to carry out experimental research on its single particle effect In the case of lacking the finished products of HfO<sub>2</sub>-based FeFET devices, using the device-hybrid simulation method to study the HfO<sub>2</sub>-based FeFET single-particle effect is a necessary and feasible content for the research on HfO<sub>2</sub>-based FeFET single-particle effects. In this paper, the device-circuit simulation method is used to build a read-write circuit of HfO<sub>2</sub>-based ferroelectric field-effect transistor. The change of read and write data after a single particle is incident on a ferroelectric field effect transistor memory cell and a sensitive node of a peripheral sense amplifier is studied, and the internal mechanism of read and write data fluctuation is analyzed. The results show that when high-energy particles enter into the drain of the ferroelectric memory cell in the read-write circuit, the memory cells in the “0” state generate electron-hole pairs, which accumulate inside the device, causing the gate electric field strength and ferroelectricity to increase, and the memory cell in the “1” state has a large fluctuation in the output transient pulse voltage signal due to the charge injection of the source, indicating that the ferroelectric memory cell has a good performance against particle flipping; when high-energy particles enter into the amplifier’s sensitive node, a collection current is generated, causing the amplifier in the state of reading “0” to turn on, and the output data to fluctuate. Owing to the fluctuation time being only 0.4 ns, the data does not have single-particle flipping energy under normal readout, and the HfO<sub>2</sub>-based FeFET read-write circuit has excellent resistance to single particles. When two beams of high-energy particles act on the drain of a ferroelectric memory cell successively in a time interval of 0.5 ns, the output data signal fluctuates more than in the case of a single beam of high-energy particles, and the final output voltage difference in the reading and writing “1” state becomes smaller.

Silicon technology has advanced through the past four decades at exponential rate both in performance and productivity. Along with the miniaturization, the power demand grew also exponentially. New technologies are studied in order to develop switches that commute faster and, in the near future, we might see an increasing number of hybrid approaches to overcome the limitations CMOS performance. The ferroelectric thin layers have been studied for memory applications, one transistor memory cell, and recently ferroelectrics have been proposed by Salahuddin and Datta as dielectric materials in transistors in order to overcome the 60mV/dec limit of the subthreshold swing (SS) in silicon Metal Ferroelectric Semiconductor Field Effect Transistors, Fe-FET. The objective of this thesis is to study the negative capacitance effect of the ferroelectrics that are integrated into the gate stack of a MOS transistor. For this purpose different Ferroelectric Field Effect Transistors (Fe-FETs) have been designed, fabricated and characterized. Due to its remarkable characteristics, like low temperature deposition, medium-k and low leakage current, vinylidene fluoride trifluorethylene, P(VDF-TrFE), an organic ferroelectric copolymer, of 100 nm and 160 nm thickness was integrated into several MOS devices. Three devices were fabricated, a metal-ferroelectric-oxide-semiconductor transistor, a metal-ferroelectric-metal-oxide-metal capacitor and a metal-ferroelectric-metal-oxide-semiconductor transistor. The internal metal was introduced in-between the two dielectrics so that the potential at that point could be probed. For the first time, subthreshold slopes as low as 48mV/dec were obtained over more than three decades of drain current. The polarization was accurately extracted and the S-shape polarization and the negative slope could be observed. The polarization presented both hysteresis and negative slope polarization. A first-order model, that can accurately characterize a Fe-FET without the negative capacitance effect, was developed and validated with the measurements. Furthermore, a model for predicting the subthreshold slope improvement in case of the negative capacitance transistor, based on the Landau's ferroelectric parameters, was presented. Among others, two possible applications of the ferroelectric transistor are highlighted, one a temperature sensor using the metal-ferroelectric-metal-oxide-semiconductor device and the other one is a Schmitt trigger based on the metal-ferroelectric-oxide-semiconductor transistor.

A multiple-input multiple-output (MIMO) wireless communication system is one of prominent systems for realizing high data-rate transmission services highly demanded in the future wireless communications. It can provide a significant performance enhancement to the wireless communications, including increased data rates through a multiplexing gain, an enhanced error probability through a diversity gain, and cancellation of multiple access interference through smart antennas. However, for such system employing coherent receivers, an accurate channel state information is crucially needed. These performance advantages and challenge, respectively, are the motivations of this dissertation. In the first part of this dissertation, a novel smart antenna system for interference canceling receivers in direct-sequence code-division multiple access (DS-CDMA) systems is proposed. This proposed scheme only exploits the spreading codes of users as the information forits weight adjustment for controlling its beam. This proposed scheme is also robust to the in-beam interference, especially in the near-far effect situation. Convergence and error probability performance analysis is also carried out. Theoretical and simulation results indicate that the proposed scheme outperforms the existing works. In the second part of this dissertation, novel channel estimators for space-time (ST) coded MIMO systems and for space-frequency coded MIMO-orthogonal frequency-division multiplexing (OFDM) systems are proposed, respectively. For the first systems, the novel pilot-embedding approach for joint channel estimation and data detection is first proposed. The unconstrained maximum likelihood (ML) and linear minimum mean square error (LMMSE) channel estimators are then proposed. Mean square error (MSE) of the channel estimation, Cramer-Rao lower bound, and Chernoff's bound of bit error rate for ST codes are analyzed for examining the proposed scheme's performances. The optimum power allocation is also investigated. Theoretical and simulation results show that a code-multiplexing based structure for the data-bearer and pilot matrices is the best among all other structures for nonquasi-static channels. For the second systems, a generalization of the proposed pilot-embedding scheme as well as the corresponding least square (LS) channel estimation and ML data detection are first proposed. Then, LS and adaptive LS FFT-based channel estimators are proposed to improve the performance of such channel estimator. The effect of model mismatch error for non-integer multipath delay profiles and MSE of these channel estimators are analyzed. The optimum number of taps for the adaptive LS FFT-based channel estimator is also determined. Theoretical and simulation results indicate that the adaptive LS FFT-based channel estimator is the best among all other channel estimators

Lab-on-a-Chip technology promises many advantages compared to existing medical diagnostic tools including better and improved performance, portability, reliability and cost reduction. The Lab-on-a-Chip technology changed the traditional way by which biological samples are inspected in laboratories during analyses. A Lab-on-a-Chip is composed of four main parts; actuation, sensing, electronics and microfluidic packaging. Typically, hybrid technologies are used for the four parts, which represent difficulties in integration and increased cost. On the other hand, Complementary Metal Oxide Semiconductor (CMOS) technology allows the use of a single homogeneous technology to develop a fully integrated lab-on-a-chip. CMOS technology is a very well-established mass-production and cheap technology. Therefore, any viable Lab-on-a-Chip based on CMOS technology will have direct commercial value and application. This tutorial will cover the following aspects: • Quanttive, the four main parts of the Lab-on-a-chip (i.e. Actuation, Sensing, Read-out circuit and microfluidic packaging) • Concepts and State of the art in the area of CMOS Technology • Survey of the most common Lab-on-a-Chip techniques based on CMOS technology • Lab-on-a-chip architectures used for different biomedical applications, such as: DNA, PCR, biocells identification and characterization • Challenges and Future trends face the CMOS Based Lab-on-a-chip technology • The tutorial also will present the research results and microsystems that are developed and funded by Information Technology Industry Development Agency (ITIDA), Egypt, Project titled “A Microfluidic platform for liver cancer cells identification and characterizations”.

Complementary metal oxide semiconductor (CMOS) technology offers batch manufacturability by ultra-large-scaleintegration (ULSI) of high performance electronics with a performance/cost advantage and profound reliability. However, as of today their focus has been on rigid and bulky thin film based materials. Their applications have been limited to computation, communication, display and vehicular electronics. With the upcoming surge of Internet of Everything, we have critical opportunity to expand the world of electronics by bridging between CMOS technology and free form electronics which can be used as wearable, implantable and embedded form. The asymmetry of shape and softness of surface (skins) in natural living objects including human, other species, plants make them incompatible with the presently available uniformly shaped and rigidly structured today’s CMOS electronics. But if we can break this barrier then we can use the physically free form electronics for applications like plant monitoring for expansion of agricultural productivity and quality, we can find monitoring and treatment focused consumer healthcare electronics – and many more creative applications. In our view, the fundamental challenge is to engage the mass users to materialize their creative ideas. Present form of electronics are too complex to understand, to work with and to use. By deploying game changing additive manufacturing, low-cost raw materials, transfer printing along with CMOS technology, we can potentially stick high quality CMOS electronics on any existing objects and embed such electronics into any future objects that will be made. The end goal is to make them smart to augment the quality of our life. We use a particular example on implantable electronics (brain machine interface) and its integration strategy enabled by CMOS device design and technology run path.

Summary of Research Results and Conclusions

A wireless multiple-input multiple-output (MIMO) communications transceiver is a promising candidate for next generation wireless systems. It can enhance the capacity and reliability of the communication link. MIMO is enabled by the presence of multiple transmitting antennas and multiple receiving antennas in the communication link. The benefits of MIMO communication are obtained through a combination of antenna arrays, signal processing, and coding algorithms, which adapt the link to the changing channel. In this critical review paper, a propagation-oriented viewpoint is adopted to discuss wireless MIMO. We give an overview of current research areas and discuss some open problems.

A high-performance 0.25- mu m CMOS (complementary metal oxide semiconductor) technology with a reduced operating voltage of 2.5 V is presented. A loaded ring oscillator (NAND FI=FO=3. C/sub w/=0.2 pF) delay per stage of 280 ps achieved (W/sub eff//L/sub eff/=15 mu m/0.25 mu m), which is a 1.7 X improvement over 0.5- mu m CMOS technology. At shorter channel lengths (0.18 mu m), a CMOS stage delay of 38 ps for unloaded inverter ring oscillators and 185 ps for loaded NAND are demonstrated. A reduced operating voltage in the range of 2.2-2.5 V is chosen to optimize performance without compromising reliability. Shallow junctions with abrupt profiles are used to minimize device series resistance as well as gate-to-source/drain (S/D) overlap capacitance. Dural poly (n/sup +/ and p/sup +/) gates are used to avoid buried-channel operation pFETs, resulting in superior short-channel characteristics. Poly and S/D sheet resistances are lowered, using a thin salicide (TiSi/sub 2/) process.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

The increasing demand of integration density improvement and battery-powered device efficiency reduced complementary metal-oxide semiconductor (CMOS) technology node. In the technology of CMOS, the components are mainly affected with leakage power, dynamic switching power, short circuit power, gate oxide tunneling leakage current, sub threshold leakage current, and so on. To reduce the above limitations, design of high efficient low power static logic circuit using shorted-gate (SG) fin field-effect transistor (FinFET) based INput DEPendent (INDEP) in 22 nm CMOS technology (SLC-SG-FinFET-INDEP-22 nm CMOS) approach is proposed in this manuscript. The better selection of inputs to proposed INDEP FinFETs model is used for reducing leakage power. The efficiency of the proposed SLC-SG-FinFET-INDEP-22 nm CMOS technique is analysed using delay, power, power delay product, and stability analysis using noise margin. Thus, the proposed SLC-SG-FinFET-INDEP-22 nm CMOS has attained 21.31%, 41.47% and 12.7% lower delay, 20.87%, 34.5% and 22.41% lower power and 4.5%, 25.7% and 32.11% higher speed than existing methods static logic circuit input-controlled leakage restrainer transistor in 22 nm CMOS (SLC-ICLRT-22 nm CMOS), static logic circuit using self-control leakage-suppression block in 22 nm CMOS technology (SLC-SCLSB-22 nm CMOS), and static logic circuit using computational digital low dropout in 22 nm CMOS technology (SLC-CDLDO-22 nm CMOS) methods, respectively.

In this contribution we propose and investigate a multiple-input multiple-output (MIMO) wireless communications system, where multiple receive antennas are distributed in the area covered by a cellular cell and connected with the base-station (BS). We first analyze the total received power by the BS through the distributed antennas, when assuming that the mobile's signal is transmitted over lognormal shadowed Rayleigh fading channels. Then, the outage probability of the distributed antenna MIMO systems is investigated, when considering various antenna distribution patterns. Furthermore, space-time coding at the mobile transmitter is considered for enhancing the outage performance of the distributed antenna MIMO system. Our study and simulation results show that the outage performance of a distributed antenna MIMO system can be significantly improved, when either increasing the number of distributed receive antennas or increasing the number of mobile transmit antennas.

FPGA-based prototyping is nowadays common practice in the functional verification of hardware components since it allows to cover a large number of test cases in a shorter time compared to HDL simulation. In addition, an FPGA-based emulator significantly accelerates the simulation with respect to bit-true software models. This speed-up is crucial when the statistical properties of a system have to be analyzed by Monte Carlo techniques. In this paper we consider a multiple-input multiple-output (MIMO) wireless communication system and show how integrating an FPGA accelerator in the software simulation framework is key to enable the development of complex hardware components in the receiver, from algorithm all the way to chip testing. In particular, we focus on a MIMO detector implementation based on the depth-first sphere decoding algorithm. The speed-up of up to 3 orders of magnitude achieved by hardware-accelerated simulation compared to a pure software testbed enables an extensive fixed-point exploration. Furthermore, it allows a unique characterization of the system communication performance and the MIMO detector run-time characteristics, which vary for different configuration parameters and operating scenarios and hence require a thorough investigation.

Nearly sixty years back when Jack Kilby built the first integrated circuit (IC), it was also the beginning of today's advanced and matured complementary metal oxide semiconductor (CMOS) technology whose arts and science of miniaturization has enabled Moore's Law to double up the number of devices in a given area in every two years. It has also been possible because CMOS technology has consistently adopted new materials and processes. High performance (data processing speed in computational devices), energy efficiency (for portable devices) and ultra-large-scale-integration (ULSI) density - all these features have been added to every major technology generation in additive manner. As we go forward and embrace Internet of Everything (IoE) where people, process, device and data are going to be seamlessly connected, we may want to ask ourselves a few fundamental questions about the future of CMOS electronics, enabling role of CMOS technology, potential benefits and application opportunities. Physically flexible electronics are increasingly getting attention as a critical and impactful expansion area for the general area of electronics. Many exciting demonstrations have been made to point out to its powerful prospect. Due to the paradox that traditional crystalline materials based electronics are useful in data management but they are naturally rigid and bulky, most of the researchers have resorted to two strategies: (i) non-silicon based fully flexible system with limited functionality and (ii) hybrid flexible electronic system with off-the-shelf ICs for data management. We do not consider this paradox is fundamental and a block-by-block approach using traditional CMOS technology can allow us to build fully flexible CMOS electronic systems [Fig. 1].

With the increasing challenges facing silicon complementary metal oxide semiconductor (CMOS) technology, emerging non-volatile memory (NVM) has received extensive attention in overcoming the bottleneck. NVM and computing-in-memory (CiM) architecture are promising in reducing energy and time consumption in data-intensive computation. The HfO2-doped ferroelectric field-effect transistor (FeFET) is one of NVM and has been used in CiM digital circuit design. However, in the implementation of logical functions, different input forms, such as FeFET state and gate voltage, limit the logic cascade and restrict the rapid development of CiM digital circuits. To address this problem, this paper proposes a Vin–Vout CiM unit circuit with the built-in state of FeFET as a bridge. The proposed unit circuit unifies the form of logic inputs and describes the basic structure of FeFET to realize logic functions under the application of gate-source voltage. Based on the proposed unit circuit, basic logic gates are designed and used to realize CiM Full Adder (FA). The simulation results verify the feasibility of FeFET as the core of logic operations and prove the scalability of FeFET-based unit circuit, which is expected to develop more efficient CiM circuits.