Switching characteristics of generalized array multiplier architectures and their applications to low power design

Abstract

This paper presents several new array multiplier architectures for reducing switching activity in general digital signal processing (DSP) applications. A cellular structure is described which can be used to obtain any array multiplier suitable for a given application. The switching activity at the output nodes of the cells in this structure is analyzed and compared with a tree multiplier based on 4:2 compressors. It is shown that the relative improvement in power is a function of statistical properties of the signal and most structures out-perform all others for specific signal conditions. It is also shown that selection of appropriate array architecture can give up to 49% reduction in switching activity compared to a tree multiplier, and more than 3 times less switching activity compared to the widely used least-significant-bit-first array multiplier for commonly occurring situations. We also outline applications of the proposed structures to the areas of low power quantization, reconfigurable computing and high-level synthesis for low power.