Surface layer characterizations and sintering time effect on electrical and giant dielectric properties of (In0.05Nb0.05)Ti0.9O2 ceramics

Abstract

In3+ and Nb5+ co-doped TiO2 (INTO) ceramics were sintered at 1400 °C for 5 and 10 h. The room temperature dielectric permittivity of the as-fired INTO ceramics significantly decreased from ε′≈ 7824 to 4669 (at 1 kHz) as sintering time increased, while the microstructure changed slightly. The corresponding loss tangent (tanδ) values were ≈ 0.040–0.047. The resistance of the insulating part and associated conduction activation energy greatly increased with increasing sintering time, corresponding to an increase in the breakdown voltage (Eb). After removing the outer surface layer, Eb was greatly reduced from 104 to 101 V/cm, corresponding to the large increase in tanδ (≈ 0.3–0.4) and ε′ (≈ 105–106). Very high ε′≈ 50,000 with low tanδ≈ 0.06 can be achieved by annealing the polished samples in air, indicating the important role of the surface layer in controlling the dielectric and electrical properties of INTO ceramics. Characterizations revealed that the formation of an insulating surface layer of the as-fired INTO ceramics may not be associated with the chemical compositional gradients of either the Ti3+ or oxygen vacancies. It was suggested that the inner and outer surface regions of INTO ceramics may consist of the same phase but with a slightly different composition.