Suppression of crosstalk by using backside deep trench isolation for 1.12μm backside illuminated CMOS image sensor

As CMOS image sensors continuously scale down, random telegraph noise (RTS) has become a more and more important consideration. In this paper, significant reduction of RTS is achieved by optimizing the deep trench isolation (DTI) process for backside illuminated CMOS image sensor (BSI).

A novel phase-detection auto focus (PDAF) technique for incident 850 nm plane wave is demonstrated using Ge-on-Si layer and deep trench isolation (DTI), which are locally arranged on light receiving surface (LRS) of crystalline silicon (c-Si). No metal light shielding film (LSF) for pupil division is formed. The key concept of the present work for PDAF is to perform the pupil division by the locally arranged Geon-Si layer in a pixel according to incident angle. The present pixel is based on a back-side illuminated CMOS image sensor pixel; the pixel pitch is 1.85 μm and the thickness of c-Si is around 3 μm. The simulation, based on three-dimensional finite difference time domain (3D-FDTD) method, shows that the external quantum efficiency (EQE) of the present pixel exhibits above 44.3 % with the maximum of 76.0 % for incident angles of - 30° to + 30°, owing to the selectively arranged Ge-on-Si layer; it exhibits 3.6 times improvement in the EQE at normal incidence compared to that of current state-of-the-art pixel with half metal-shielded aperture; the EQE is 49.2 % and 13.8 %, respectively. The present technique can enhance the accuracy of AF under low-illuminated condition.

In this work, we have utilized finite difference time domain (FDTD) simulation to investigate the crosstalk behavior with the deep trench isolation (DTI) shape and radius of curvature (RoC) of microlens of pixels arrayed in a Bayer pattern. For blue illumination of 400 nm, the sum of optical and spectral crosstalk is lower for DTIs with values of W <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ratio</inf> is greater than 1; for green illumination of 550 nm, we got a similar result when the values of W <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ratio</inf> is below 1. The higher generation of electron hole pairs (EHPs) deep inside silicon (Si) causes a rise in the electrical crosstalk with larger W <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ratio</inf> values with blue illumination of 400nm. The optical and spectral crosstalk cumulatively increases with microlens having a higher RoC due to the wider spread of illumination overlaps with the DTI surface and eventually leaks into neighbor pixels.

For most people, Apple’s introduction of backside-illuminated (BSI) CMOS image sensors (CIS) in their iPhone4 may have been the first time they became aware of this technology. Compared with traditional front-illuminated CMOS, light in a BSI CIS can strike the photocathode directly without passing through wiring layer. Thus, photon absorption efficiency increases from 60% to 90%. As the size of the CIS decreases, this performance improves. Now, BSI CIS are widely used in digital cameras, smartphones, etc. However, placing the active matrix transistors behind the photocathode gave rise to a host of new problems, such as cross-talk, which would cause noise and dark-current, and color mixing between adjacent pixels. Solving these problems calls for a low-cost solution in the etch process used in volume production. Etching a BSI CIS film stack is very complex. The etch must pass through approximately half a micron of silicon oxide or nitride, a high-k film and more than 2 microns of silicon. As many of the pre-layers have been planarized, the thickness of oxide/nitride film or silicon film is very variable (typically more than 10%). High etch selectivity and precise time control are therefore necessary. The Applied Materials Centura® AdvantEdge™ Mesa™ etch chamber maintains a high silicon etch rate while preserving a vertical sidewall profile. The oxide/nitride etch rate was acceptable; it also exhibited high selectivity and minimal micro-loading. This chamber was therefore the best choice for this application. The EyeD® endpoint system was used to monitor the interface of the film to control process time. The backside grounding layer (application 1) is similar to pad1. To eliminate deposition voids, a very tapered profile was required (70º+/-5°). The SF6/Cl2/C4F8 recipe could achieve that profile, but had very high silicon etch rate. It would create serious sub-trench issues when the high-k layer was punched through. Its process window was also very marginal. CF4/CHF3 was tested as an alternative, but produced excessive polymer deposition. The profile of high-k became unacceptably tapered. We ultimately used a two-step approach to precisely control polymer deposition and this approach produced a very good profile. For the backside interconnection layer (application 2), tapered profiles were also required. More importantly, the etch had to pass through more than 2 microns of silicon while retaining an approximately 70° profile angle. The gas ratio had to be precise, and pressure was kept at a mid-level. The final profile, which was very good, was superior to that achieved by our competitors. The silicon thickness is very variable because of the limitations of the planarization process. For best production flexibility, we use the EyeD optical endpoint system. Initially, the signal was very weak when the process was deep in the silicon. However, a very robust endpoint was obtained by fine-tuning the EyeD algorithm.

BackSide-Illuminated (BSI) CMOS Image Sensors (CISs), with developed performance on quantum efficiency and sensitivity, have been applied for aerospace missions and gradually replaced FrontSide-Illuminated (FSI) CISs. Two types of BSI CISs with different epitaxial layer thicknesses were irradiated by 14-MeV neutron up to 3.40 × 1011 n/cm2 to analyze the degradation induced by neutron irradiation. Dark current, dark current distribution, full well capacity, and spectral response were tested before and after the neutron irradiation and at different annealing time points with various temperatures. The results were analyzed to characterize the degradation introduced by the unique backside passivation layer, and the converse illuminated direction. The interface states induced by displacement damage effects at the backside passivation layer were considered as a novel origin of dark current which was not involved in FSI CISs.

A novel low cost backside illuminated CMOS image sensor structure is proposed in this research. By using thin wafer handling technology, the wafer is thinned down to less than 5 μm and no TSV and direct bonding process are needed in this low cost solution. The processed backside illuminated CMOS image sensor is then stacked with analog to digital conversion chip and image signal processor by 3DIC technology. A 3-Mega pixel image is captured and demonstrated in this research.

In this research, a new structure and process integration for backside illuminated CMOS image sensor by using thin wafer handling technology is proposed. First of all, the wafer of a 3 Mega pixel CMOS image sensor is temporary bonded to a silicon carrier wafer with thermal plastic material and ZoneBond technology. Then the CMOS wafer is thinned down to few microns to detect the light from the backside. The backside is then permanently bonded to a glass carrier substrate with a transparent thermal set bonding material. After the glass permanent bonding process, the temporary bonded silicon carrier could be removed. Cu/Sn micro-bump is fabricated at the front-side of the CMOS image sensor, thus no TSVs are needed in the proposed structure. A 3 Mega pixel CMOS wafer with micro-bumps bonded on 500µm-thick glass wafer is demonstrated. Void-free bonding is obtained both in temporary bonding and permanent bonding processes. The thickness of the CMOS image sensor wafer is less than 10 µm after thinning and the total thickness variation is around 1 µm. Thermal plastic material is used for temporary bonding because it flows during bonding process and resulted in excellent planarization. From the cross-section SEM image, Cu/Sn micro-bump is formed at the front-side of the CMOS image sensor and the ENIG UBM is formed on the front side of the Analog-to-Digital Conversion wafer. A 3 Mega pixel image is captured and demonstrated in this research. The proposed backside illuminated CMOS image sensor structure and process integration are processed in wafer level, therefore enabling a low cost technology which can be manufactured using existing infrastructure. By using thin wafer handling technology, direct fusion bond and TSV processes are not needed which provides a low cost wafer level solution.

In this research, a new structure and process integration for backside illuminated CMOS image sensor by using thin wafer handling technology is proposed. First of all, the wafer of a 3 Mega pixel CMOS image sensor is temporary bonded to a silicon carrier wafer with thermal plastic material and ZoneBond technology. Then the CMOS wafer is thinned down to less than 5 μm for light detection from the backside. After thinning process, the backside is permanently bonded to a 500μm-thick glass carrier substrate with a transparent thermal set bonding material. After thinning, the total thickness variation of 1μm is obtained because the thermal plastic material flow during bonding process resulted in excellent thickness uniformity. The proposed backside illuminated CMOS image sensor structure and process integration are processed in wafer level, therefore enabling a low cost technology which can be manufactured using existing infrastructure. In the assembly process of CMOS image sensor stack, firstly the analog-to-digital conversion chip was stacked onto the image signal processor chip by thermal compression bonding. Optimized bonding conditions of 250 °C/5 sec under the bonding force of 13N were chosen and determined. Subsequently, after the stack of analog-to-digital conversion chip onto the image signal processor chip, the CMOS image sensor chip was bonded onto the image signal processor/analog-to-digital conversion stack. To connect all the solder bumps between CMOS image sensor and analog-to-digital conversion chip, the higher bonding force of 18N was selected. Joined-well solder joints between these two chips could be achieved. Finally, the stacked CMOS image sensor module was attached to a print circuit board by adhesive material and wire bonding was conducted to finish the electrical connectivity between CMOS image sensor stack and print circuit board.

In this study, a back-side illuminated CMOS image sensor (BSI-CIS) without through-silicon via (TSV) is developed with thin wafer handling combination with ultra-wafer thinning technologies. The CIS wafer is implemented front-side processes then temporarily bonded on a Si carrier by Brewer Science adhesive with ZoneBOND™ technology applied. The ZoneBOND™ technology provides a promising solution for thin wafer handling with temporary bonding, wafer thinning, thin wafer processes, and de-bonding. After thinning, the CIS backside is bonded with glass wafer, and the Si carrier is removed using solvent dipping for de-bonding. The thickness of BSI-CIS without TSV is less than 5μm, which is visible light transparent to meet the back-side illumination requirement. Cu/Sn bumps with 50μm size are formed with the bump height uniformity less than 5% in wafer level. The completed BSI-CIS is then assembled on Si substrate. There are totally 400 bumps in this test vehicle design. The Cu/Ni/Au UBMs on Si substrate bonded with Cu/Sn bumps on CIS is conducted by thermal compression bonding. The wafer-level package of TSV-less BSI-CIS has been successfully developed and demonstrated, stacked module is accomplished and passed 1000 cycles of -55°C~125°C TCT in the paper.

Backside illuminated CMOS image sensors with a 3D stacked architecture, where the pixel array is attached on top of the logic circuit, was introduced and have just come to the market. Image sensor featuring 3D stacking was realized by connection between the interconnect layers of the top and bottom parts using vertical type through-silicon via (TSV).1 Cu bonding technology for 3D integration has been studied and widely applied.2As Wafer-to-wafer bonding process is now being used widely and matured through the production of Backside illuminated CMOS image sensors, Copper-copper bonding provides an attractive route to 3D stacked image sensor since it creates a strong metal bond and enables vertically electrical connection during the bonding process.Specific pre-bonding surface conditioning is necessary to insure high bonding quality of patterned Cu wafers using Cu-Cu non-thermo compression bonding for wafer-to-wafer 3D stacking. Surface preparations for the hybrid fusion bonding such as removal of Cu oxide, Cu surface protection and optimized CMP planarization patterned Cu surfaces have been studied,3 but the study on plasma condition for hybrid fusion bonding is relatively a few. The work described here is investigating of the plasma-related Cu patterned hybrid surface preparation under different plasma conditions.The main physical mechanisms about Cu-Cu non thermal compression bonding are spontaneous adhesion of hydrophilic surfaces followed by Cu diffusion across the bonding interface when Cu-Cu contact is reached (diffusion bonding) have been previously reported.4 The property of Cu dielectric diffusion barriers used in ULSI is hydrophobic. For the efficient bonding of hydrophobic-hydrophobic layers, surface conversion process is introduced.5 In the case of Cu-patterned hybrid bonding in typical Cu metallization layer in ULSI, Trade-off between dielectric diffusion barrier and Cu cannot be avoidable by surface conversion process.During the Cu-patterned hybrid bonding development, the common electrical failed areas were found.To investigate the failure mechanism, influence of plasma condition on the activation of wafer surface and bonding quality was studied. The wafer surface was examined by X-ray photoelectron spectroscopy (XPS), surface roughness, and observation of differential work function uniformity over a full wafer area caused by plasma-induced charge.6The ChemetriQ NVD inspection system from Qcept Technologies was used to inspect differential work function uniformity.After implementing plasma treatment applied in bonding process, Non-uniformity of a charge map and different plasma influence over a full wafer area were shown, even there was no difference through the AFM analysis. For the optimization of the bonding process, especially plasma process, a method to examine the surface condition in this paper makes it possible to monitor the plasma process and improve bonding process

Study of dark current random telegraph signal in proton-irradiated backside illuminated CMOS image sensors

Proton irradiation effect mechanism of backside illuminated CMOS image sensors applied to FGS

The measurement of the charge collection properties at the back surface of a backside illuminated CMOS image sensor optimised for soft X-ray detection is presented. Further investigation of the CIS221-X at the BESSY-II synchrotron has enabled the properties of the back surface partial charge collection layer to be determined. There is agreement between the measured properties and both existing models inferred from quantum efficiency testing conducted on the detector and other detectors with similar back surface processing. The partial charge collection region, close to the back surface of the detector, has a large impact on the behaviour exhibited by the X-ray detector when observing very soft X-rays. Determination of these effects is an important step towards the use of the CIS221-X for scientific applications.

We have developed a compliant bump technology for 3D chip stacking with the same number of inter-chip connections as that in a VGA (video graphic array, 640 times 480). Using this technology together with a through-Si via (TSV) technology, we demonstrate a prototype of back-side illuminated CMOS image sensor, in which a very-thin rear-illuminated photodiode array is electrically connected to the CMOS readout circuit at a pixel level.

In this research, a backside illuminated CMOS image sensor (BSI-CIS) without through-silicon via and TSV based Si interposer are developed with thin wafer handling technology. The BSI-CIS wafer is implemented front-side processes then temporary bonded on a Si carrier by using ZoneBOND™ technology. After thinning, the CIS backside is bonded with glass wafer, and the Si carrier is removed using solvent dipping for de-bonding. The thickness of BSI-CIS without TSV is less than 5um, which is visible light transparent to meet the back-side illumination requirement. TSV fabrication, void-free TSV filling, bumping, wafer thinning, thin wafer handling and backside RDL formation are well developed and 30um TSV, 60um thin wafer have been successfully integrated to Si interposer. Cu/Sn bumps with 50μm size are formed with the bump height uniformity less than 5% in wafer level. The wafer-level package of BSI-CIS and TSV based Si interposer have been successfully developed and demonstrated, the characterization results of three layer stacked module is also disclosed in the paper.