Superconductor-normal metal-superconductor process development for the fabrication of small Josephson junctions in ramp type configuration

Abstract

At PTB, a fabrication process has been developed in SNS Nb/PdAu/Nb technology for the verification of small Josephson junctions (JJs) in the deep sub-micron range to enable the implementation of JJs as active elements in highly integrated superconducting circuits. Two steps of this technological development are described with regard to appropriately designed circuit layouts of JJ series arrays (JJAs), the first one in a conventional window type junction (WTJ) configuration and the second one in a ramp type junction (RTJ) configuration. Test circuits of JJAs containing up to 10 000 JJs have been fabricated and experimentally tested. In WTJ configuration, the circuits proved to be sensitive to external perturbing effects affecting the stability of circuit operation. In contrast to that, in RTJ configuration, the circuits realized showed correct function and a high grade of reliability of operation. To produce RTJ circuits, the technology parameters have been set to realize JJs with contact areas of A = 0.25 µm × 1.3 µm. At a thickness of the PdAu normal metal layer of d = 40 nm, the values achieved for the critical current density and for the product of critical current and normal state resistance are about jc = 200 kA cm-2 and about IcRN = 21 µV.