Abstract
Super junction (SJ) concept is attractive for power devices because of its advantage for improving the tradeoff between the breakdown voltage (BV) and the on resistance (R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</sub> ). It is an acknowledged wish to apply the SJ concept to LDMOS for the power integrated circuits (PICs). However, the conventional SJ LDMOS is no practical due to the influence of the fabrication process, charge imbalance, and junction termination, etc. This paper introduces the key technologies for the SJ LDMOS based on our researched SJ device named SLOP (Surface Low On-resistance Path) LDMOS, aiming to offer applicable lateral SJ device for the PICs.
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