Subthreshold behavior of dual-bit nonvolatile memories with very small regions of trapped charge

Abstract

We propose an analytical approach to investigate the electrostatic impact of very small charged regions in the gate dielectric of dual-bit nonvolatile memory cells based on discrete trapping sites, such as SONOS, NROM, or nanocrystal memories. Our model is based on the analytical solution of the Poisson equation for the surface potential in a fresh memory cell in subthreshold conditions. Then, we evaluate the effect of a small pocket of trapped charge on the surface potential using the superposition principle. Our proposed model is particularly accurate for small charged regions, down to the charged length L2sime10 nm and for charge density up to Qsime1013 cm-2. In addition, the proposed model represents a complementary approach to a previously developed model which was suitable for larger charged regions. Relevant consequences of the asymmetric charging of the storage layer on the electrical characteristics of discrete-trap memories are thoroughly analyzed. An analytical expression for the subthreshold slope factor S, the threshold voltage Vth, and a method for extracting an effective distribution of charges from the transfer characteristics are derived