Substrate Engineering by Hexagonal Boron Nitride/SiO2 for Hysteresis‐Free Graphene FETs and Large‐Scale Graphene p–n Junctions

Abstract

We have explored an approach for the fabrication of intrinsic and hysteresis-free graphene field-effect transistors (FETs) and for the construction of graphene p-n junctions based on substrate engineering by hexagonal boron nitride (h-BN)/SiO2. The effect of various interfaces on the performance of the graphene FETs was systematically studied by constructing four types of graphene devices (graphene/SiO2 FETs, graphene/h-BN FETs, h-BN/graphene/SiO2 FETs, and h-BN/graphene/h-BN FETs). Graphene/SiO2 FETs and h-BN/graphene/SiO2 FETs always exhibit large hysteresis before and after annealing, whereas graphene/h-BN FETs and h-BN/graphene/h-BN FETs show intrinsic properties after annealing. Raman measurements also indicate that graphene on a SiO2 substrate contains large amounts of p-doping, whereas that on a h-BN substrate is intrinsic. Thus, the graphene/h-BN interface gives intrinsic and hysteresis-free graphene FETs, whilst the graphene/SiO2 interface affords p-doping and a hysteresis effect in the graphene FETs. This result is because h-BN serves as an insulation layer, which prevents charge trapping between the graphene and the charge traps at the graphene/SiO2 interface, which cause the hysteresis. In addition, the negligible electrostatic doping of h-BN into graphene also ensures the intrinsic and hysteresis-free properties of graphene/BN/SiO2 FETs. Moreover, benefitting from the p-doped and intrinsic features of graphene on SiO2 and h-BN substrates, respectively, large-scale graphene p-n junction superlattices with great potential difference are constructed and integrated into photodetector arrays by substrate engineering with h-BN/SiO2. Efficient hot carrier-assisted photocurrent was generated by laser excitation at the junction under ambient conditions.