Abstract

In today's era, the very large scale integration (VLSI) industry focuses on area, speed, and power dissipation. Scaling down the metal oxide semiconductor field-effect transistor (FET) has helped to maintain the previously mentioned requirements and to withhold Moore's law. Scale down went well until the metal oxide semiconductor FET entered the nanometer regime. In the nanoscale region, short channel effects like drain-induced barrier lowering, the hot electron effect, impact ionization, velocity saturation, etc., dominated the performance of the device. Hence, for a couple of decades researchers were trying to provide an alternate solution in the form of the tunnel FET, nanowires, and junctionless transistors, although the proposed devices have their own set of advantages like lower subthreshold slope, higher ION /IOFF , etc. Of these devices, the tunnel FET consists of drawbacks that cannot be ignored, for example, difficult fabrication and higher Miller capacitances. Hence, this work focuses on the design of the junctionless transistor. Another concern of researchers is the failure of silicon at nanoscale due to decrement in the mobility of its charge carriers. Alternate solutions are two-dimensional materials like graphene, transition metal dichalcogenides, and black phosphorus. In this chapter, different transition metal dichalcogenide materials based on the junctionless transistor are proposed. Simulation is performed on the Silvaco ATLAS TCAD. The different transition metal dichalcogenide materials compared are MoS2, MoTe2, MoSe2, WS2, and WSe2. For all of the transition metal dichalcogenide materials, device properties (bandgap, potential, electric field), quantum effects (density of states, transmission probability), IDS -VGS , and linearity properties are studied. This chapter also illustrates the effect of variation in dielectric oxide on the performance of transition metal dichalcogenide materials.

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