Abstract
This article provides an insight into the electrical and thermal performance improvement of a junctionless vertical super-thin body (JL VSTB) FET based on dimensional and material optimization in its shallow-trench isolation (STI) wall and contact/side isolations with the aid of a properly calibrated TCAD tool. The lowering in STI wall thickness ( tSTI ) and contact isolations’ height ( hi ) effectively improves off-state current ( Ioff ) and on current ( Ion ), respectively. More interestingly, by inducing fringing field effect on channel, the material of STI wall and side isolations exhibits a crucial effect on Ioff and Ion , respectively. On the other hand, the thermal analysis based on the self-heating effect (SHE) reveals that compared to hi , tSTI has a much more prominent control over the thermal response of the device. Such a nature originates because unlike hi , tSTI -variation directly causes dimensional change in the principal heat sink (substrate) of the device. In addition, an excellent improvement in all the thermal parameters is shown by employing high thermal conductivity material in STI/all isolations. Finally, based on low lattice temperature profile, the most suitable sets of tSTI and hi for low-power (LP) and high-performance (HP) applications are suggested in accordance with Ioff and Ion characteristics, respectively.
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