Abstract
In this Study, a Wallace tree adder and a group of comparators were employed to design the stochastic flash analogue to digital converter (ADC). In order to demonstrate how power, and area may be decreased utilizing offset voltage in design, a comparison between stochastic flash ADC and Resistor ladder flash ADC is presented in the study. A resistor string is used to set each comparator’s trip point in a standard resistor ladder flash ADC. Random comparator offsets are compressed into digital cells by a stochastic flash ADC. A wide range of comparator offsets are compressed into digital cells by a stochastic flash ADC. A wide range of comparator offset is produced when using comparators that are implemented as digital cells. This is typically seen as a drawback, however in our situation the wide standard deviation of offset is employed to define the input signal range. The reference voltage is lower and the analog signal is always ‘‘ 1’’ if the input offset voltage of a comparator is greater than the input range of its comparator group. To produce digital output, one uses the Wallace tree adder. In a 90nm CMOS process, a stochastic flash ADC has been implemented.
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