Step voltage with periodic hold-up etching: A novel porous silicon formation

Abstract

A novel etching method for preparing light-emitting porous silicon (PS) is developed. A gradient steps (staircase) voltage is applied and hold-up for different periods of time between p-type silicon wafers and a graphite electrode in HF based solutions periodically. The single applied staircase voltage (0–30 V) is ramped in equal steps of 0.5 V for 6 s, and hold at 30 V for 30 s at a current of 6 mA. The current during hold-up time (0 V) was less than 10 μA. The room temperature photoluminescence (PL) behavior of the PS samples as a function of etching parameters has been investigated. The intensity of PL peak is initially increased and blue shifted on increasing etching time, but decreased after prolonged time. These are correlated with the study of changes in surface morphology using atomic force microscope (AFM), porosity and electrical conductance measurements. The time of holding-up the applied voltage during the formation process is found to highly affect the PS properties. On increasing the holding-up time, the intensity of PL peak is increased and blue shifted. The contribution of holding-up the applied steps during the formation process of PS is seen to be more or less similar to the post chemical etching process. It is demonstrated that this method can yield a porous silicon layer with stronger photoluminescence intensity and blue shifted than the porous silicon layer prepared by DC etching.