Abstract
Reducing the amount of power consumed by multiprocessing systems has become a critical design requirement, especially with the recent introduction of multimedia functions on mobile phones and the implementation of system-on-chip (SoC) in 65 nm CMOS. No longer able to rely on the inherent low-power performance of underlying semiconductor processes, designers must therefore find new ways of reducing power consumption. This paper describes several ways to save power consumption including dynamic voltage and frequency scaling (DVFS) and a combination of DVFS and body biasing. The paper also discusses the need for future SoCs to adopt new system architectures to overcome the effects of both frequency and voltage scaling. One approach currently finding favor is the globally asynchronous, locally synchronous (GALS) architecture.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
