Abstract

Statistical variability (SV) critically affects the scaling, performance, leakage power, and reliability of devices, circuits, and systems [1]. The good electrostatic integrity of UTB-FD-SOI transistors tolerates low channel doping and dramatically reduces the statistical variability due to random dopant fluctuations (RDF), but other sources of variability remain pertinent, including line edge roughness (LER), metal gate granularity (MGG) leading to work-function variation (WFV), oxide thickness fluctuations (OTF), and interface trapped charge due to NBTI/PBTI [2–4]. The different physical nature of these phenomena affects the spread of threshold voltage (Vth), on-current (Ion), and DIBL of the transistors in different ways, and is, for the first time, comprehensively studied here for three LOP-technology generations of n-channel UTB-FD-SOI devices with a physical gate length L G of 22, 16, and 11 nm.

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