Abstract
The effects of electrical stress on n-channel polysilicon thin-film transistors (poly-Si TFTs) with electron cyclotron resonance (ECR) plasma gate oxide have been investigated. The plasma-hydrogenerated low-temperature (/spl les/600/spl deg/C) TFT's exhibited very a small increase of threshold voltage (/spl Delta/V/sub th/<0.3 V) under the stress conditions (V/sub gs/=15 V, V/sub ds/=0 V /spl sim/15 V, and stress time=5/spl times/10/sup 4/ s). The /spl Delta/V/sub t/h was larger for the stress in the linear region than in the saturation region. It was found that the device degradation for the stress in the saturation region was caused by the hot-carriers. Increase of OFF current was maximum for the stress at V/sub gs/=V/sub ds/ while for the stress at V/sub gs/<V/sub ds/, degradation of transconductance was the dominant effect seen.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
