Stability and 2-D Simulation Studies of Avalanche Breakdown in 4H-SiC DMOSFETs With JTE

Abstract

In this paper, the stability of n-channel 4H-silicon carbide (SiC) DMOSFETs with junction termination extension (JTE) was assessed by measuring the breakdown voltage (BV) of these devices before and after bias stress at a high temperature. The BV slumped after the DMOSFET was bias stressed at 1200 V for 2 h at 175degC, and the slumped BV dynamically recovered to the prestress value during the poststress period. Computer simulation suggests that the BV slump and its recovery are dominated by the positive charge trapping/detrapping phenomena at the SiC/fleld oxide interface in the JTE structure, rather than the trapping/detrapping at the SiC/gate oxide interface in the cell structure. A positive interface charge of approximately one-third of the sheet dopant concentration of the JTE region, lowers BV by 150 V, which is the typical measured BV slump of the DMOSFETs of this paper.