Stability Analysis of a Medium Voltage Cascaded Converter System with Reduced DC-link Capacitance

Abstract

Recent development of Silicon Carbide (SiC) based Medium Voltage (MV) power semiconductor devices have paved ways to build high power MV power converters with simple two level structures. One of the critical applications of these converters are solid state transformers (SSTs) which interconnects MV grid to a low voltage (LV) grid with high frequency isolation. SSTs are usually built with multi-stage cascaded conversion structures which includes ac-dc, dc-dc, and dc-ac stages, respectively. These converter structures need an intermediate MV DC bus to function. For MV applications, the DC bus structure is designed with low inductance bus bar and MV capacitors. At medium voltage levels, it is difficult to manufacture capacitors with high capacitance values with low footprint. Therefore, MV polypropylene film capacitors with low equivalent series inductance (ESL) are often utilized to build the MV DC Bus to meet the power density requirements. The small values of the effective DC bus capacitance create stability issues for cascaded converter structures for SSTs as it becomes difficult to completely decouple different power conversion stages. This paper delves into the interaction between different power conversion stages of a MV SST while transferring power. The study shows that low capacitance value of the MV DC bus can cause instability which needs to be mitigated.