Abstract
The Square Kilometre Array Low is a next generation radio telescope, consisting of 512 antenna stations spread over 65 km, to be built in Western Australia. The correlator and beamformer (CBF) design is central to the telescope signal processing. CBF receives 6 Tera-bits-per-second (Tbps) of station data continuously and processes it in real time with a compute load of 2 Peta-operations-per-second (Pops). The correlator calculates up to 22 million cross products between all pairs of stations, whereas the beamformers (BFs) coherently sum station data to form more than 500 beams. The output of the correlator is up to 7 Tbps, and the BF 2 Tbps. The design philosophy, called “Atomic COTS,” is based on commercial off-the-shelf (COTS) hardware. Data routing is implemented in network switches programmed using the Programming Protocol-Independent Packet Processors (P4) language and the signal processing occurs in COTS field-programmable gate array (FPGA) cards. The P4 language allows routing to be determined from the metadata in the Ethernet packets from the stations. That is, metadata describing the contents of the packet determines the routing. Each FPGA card inputs a fraction of the overall bandwidth for all stations and then implements the processing needed to generate complete science data products. Generation of complete science products in a single FPGA is named here as Atomic processing. A Tango distributed control system configures the multitude of processing modes as well as maintaining the overall health of the CBF system hardware. The resulting 6 Tbps in and 9 Tbps out, 2 Pops Atomic COTS network attached accelerator occupies five racks and consumes 60 kW.
Highlights
Building correlators and beamformers (CBFs) for a large interferometer has always been a challenge because of the high data rates and the need for real-time processing
We describe a further advance that has become possible with the advent of commercial off-the-shelf (COTS) field-programmable gate array (FPGA) boards (Xilinx Alveo13) aimed for use in data centers
This is enabled by high-bandwidth memory (HBM) directly attached to the FPGA that is on the Alveo board
Summary
Building correlators and beamformers (CBFs) for a large interferometer has always been a challenge because of the high data rates and the need for real-time processing. It builds on the CASPER approach to correlators: switches for data routing and FPGAs boards for computation. An investigation of the Programming Protocol-Independent Packet Processors[14] (P4) language and hardware showed a metadata driven approach was possible This made the P4 switch just an extension of what was done in a previous FPGA system with dedicated interconnection that the authors were familiar with. An end-to-end BF or correlator incorporating filterbanks (FBs) and wavefront correction is implemented in a single FPGA for a subset of the bandwidth This is enabled by high-bandwidth memory (HBM) directly attached to the FPGA that is on the Alveo board. The I/O capacity of the Alveo card is lower than previous bespoke designs, the use of Atomic processing and P4 switching technology maximizes the compute per unit of I/O, allowing the full capabilities of the hardware to be utilized
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