Abstract
This paper discusses sputtered silicon encapsulation as a wafer level packaging approach for isolatable MEMS devices. Devices such as accelerometers, RF switches, inductors, and filters that do not require interaction with the surroundings to function, could thus be fully encapsulated at the wafer level after fabrication. A MEMSTech 50g capacitive accelerometer was used to demonstrate a sputtered encapsulation technique. Encapsulation with a very uniform surface profile was achieved using spin-on glass (SOG) as a sacrificial layer, SU-8 as base layer, RF sputtered silicon as main structural layer, eutectic gold-silicon as seal layer, and liquid crystal polymer (LCP) as outer encapsulant layer. SEM inspection and capacitance test indicated that the movable elements were released after encapsulation. Nanoindentation test confirmed that the encapsulated device is sufficiently robust to withstand a transfer molding process. Thus, an encapsulation technique that is robust, CMOS compatible, and economical has been successfully developed for packaging isolatable MEMS devices at the wafer level.
Highlights
Nowadays device packaging remains a major challenge in the micro electromechanical systems (MEMS) industry
In order to assess the feasibility of the proposed packaging technique, sputtered silicon encapsulation was built on an unpackaged MEMSTech 50g non-crossing differential capacitive accelerometer
The subsequent layer is annealed silicon, which serves as the main structural layer of the encapsulation
Summary
Nowadays device packaging remains a major challenge in the micro electromechanical systems (MEMS) industry. Many application specific MEMS devices such as accelerometers, pressure sensors, and microgyroscopes require custom packaging to function. Microsensors often require contact with the surroundings to measure air or fluid pressure, gas content, or flowing liquids, making device packaging even more challenging and expensive. On top of being geometrically complex to package, moving parts of MEMS devices are highly sensitive to damage and contamination during fabrication and packaging processes. Stringent device performance requirements have driven the need for a packaging method that is robust, manufacturable using CMOS compatible processes, and fabricated and tested. In an effort to lower packaging cost, improve yield, and comply with these requirements, many MEMS manufacturers are starting to explore wafer level packaging
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