Abstract
An embedded split-gate flash memory based on 65nm logic process technology has been developed. The design rules for split-gate flash macro's testability and reliability are discussed. An automotive grade flash memory with 100K endurance, 10 years, 125°C data retention, and 1-ppm requirement has been demonstrated with a comprehensive dielectric screen methodology. Both erase time push out and data retention dominant mechanisms are thoroughly studied with intrinsic lifetime and large sample certification. An automotive embedded split-gate flash solution in 65nm technology is ready for commercialization.
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