/spl plusmn/0.5 V/spl sim//spl plusmn/1.5 V VHF CMOS LV/LP four-quadrant analog multiplier in modified bridged-triode scheme

S.C Li,J.C Cha

doi:10.1109/lpe.2002.146743

/spl plusmn/0.5 V/spl sim//spl plusmn/1.5 V VHF CMOS LV/LP four-quadrant analog multiplier in modified bridged-triode scheme

S.C Li, J.C Cha

https://doi.org/10.1109/lpe.2002.146743

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Publication Date: Jan 1, 2002

Affiliation: National Yunlin University of Science and Technology

#Total Harmonic Distortion #Terms Of Linearity + Show 8 more

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Abstract

A new LV/LP CMOS four-quadrant analog multiplier designed in a modified bridged-triode scheme (MBTS) is presented. It provides benefits in terms of linearity, power consumption, frequency response and total harmonic distortion (THD). The fabricated chip in TSMC 0.35 /spl mu/m n-well SPQM CMOS technology has a nonlinearity error less than 0.8% over /spl plusmn/0.5 V input range under a nominal supply voltage of /spl plusmn/1.5 V, and consumes the total power dissipation of 2.7 mW only.

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