Spintronics and magnetic memory devices

Spintronics based random access memory: a review

The spin transfer torque (STT) magneto-resistive random access memory (MRAM) often uses bulk and silicon on insulator (SOI) metal oxide semiconductor (NMOS) as access device. However, the drive current reduction due to the substrate bias effect in bulk NMOS and lattice heating effect in silicon on insulator (SOI) NMOS makes them less suitable for STT MRAMs. The reduction in write current actually increases the write errors in STT MRAMs that adversely affects the reliability of STT MRAM cell. Taking these reliability concerns into account, an STT MRAM cell with fully depleted (FD) silicon carbide (4H-SiC) substrate NMOS is presented that is impervious to drive current reduction due to the substrate bias and self heating effects. The proposed STT MRAM cell with FDSIC NMOS exhibits a maximum variation of 3% in the steady state lattice temperature manifesting very low possibility of thermal fatigue and device failures. Moreover, the proposed cell offers extremely low leakage power dissipation that is almost three orders smaller than the conventional cell. The circuit level analysis of STT MRAM is done using calibrated Verilog-A models. Encouragingly, the proposed FDSIC cell demonstrates 45% improvement in write error rate over conventional FDSOI cell.

Spintronic memory has been considered as one of the most promising nonvolatile memory candidates to address the leakage power consumption in the post-Moore’s era. To date, the spintronic magnetic random access memory (MRAM) family has mainly evolved in four-generation technology advancement, from toggle-MRAM (product in 2006), to STT-MRAM (product in 2012), to SOT-MRAM (intensive R&D today), and to VCMA- MRAM (intensive R&D today). In addition, another spintronic memory, named racetrack memory (RM), proposed in 2008, has also evolved in two generations from domain wall (DW) based RM to skyrmion-based RM. On the other hand, from the architectural perspective, data transfer bandwidth and the related power consumption has become the most critical bottleneck in vonNeumann computing architecture, owing to the separation of the processor and the memory units and the performance mismatch between the two. Realization of the unity of computing and memory in the same place has opened up a promising research direction of computing-in-memory (CIM). Spintronic memory could be a promising technology to implement the CIM paradigm, owing to its intrinsic processing capability. Lots of interests have been attracted and a number of attempts have been made in this field, within both MRAM and RM. In this paper, we perform a mini review on the R&D evolution of spintronic memories: from memory to computing-in-memory. Particularly, we will introduce our recent work on advanced spintronic memories as well as CIM paradigms implemented within spintronic memories.

Industrial and academic development laboratories worldwide are working to perfect the circuit designs, fabrication methods and integration schemes required for successful commercial production of Magnetic Random Access Memory (MRAM) devices, a new kind of nonvolatile memory technology that some forecast to be a “universal” memory replacement for DRAM,SRAM and flash.Among the more important issues for MRAM cell design and fabrication are the basic configuration of the magnetic memory element (pseudospin-valve or magnetic tunneling junction, for example), the material set used to fabricate the magnetic memory element, the shape of the magnetic memory element and the patterning techniques used to fabricate the cell. Two important attributes of the MRAM cell may be unfamiliar to those with experience in other IC fabrication processes. These are the special considerations that must be taken when designing the physical shape of the magnetic memory storage element and the specific fabrication techniques that need to be applied to pattern the many layers of alloys (NiFe, for example) and metals (ruthenium, cobalt) found in the MRAM stack. Ion milling has been the historically- important method of record for fabricating low-density MRAM products for applications with limited production volumes. Now that large IDMs like IBM and Infineon, Motorola, Philips, STMicroelectronics and NEC are approaching MRAM processing in earnest, the perceived manufacturing limitations of ion milling have motivated development teams to consider other methods, including wet etch, plasma etch and damascene for patterning MRAM stacks. We review here the theory of MRAM operation, discuss the interaction between the physical shape of the MRAM cell and its ability to store binary information, present the various options for patterning MRAM stacks as championed by the major IDMs with public MRAM programs, and summarize some of our own work on plasma etching MRAM devices.

Due to nearly zero leakage power consumption, non-volatile magnetoresistive random access memory (MRAM) is becoming one of the promising candidates for replacing conventional volatile memories (e.g. SRAM and DRAM). In particular, emerging spin-orbit torque (SOT) MRAM is considered to outperform spin-transfer torque (STT) MRAM due to its fast switching, separate read/write paths, and lower energy dissipation. However, the SOT-MRAM technology is still in its infancy; one key design challenge is that the control of SOT-MRAM, which involves three terminals, is more complicated compared with STT-MRAM. In this paper, we propose a novel MRAM write scheme called PRESCOTT1, where the "1" and "0" data values can be written into memory cells through the SOT and STT, respectively. As a result, the write current is unidirectional rather than bi-directional, which addresses the control complexity. Using this unidirectional write scheme, we design a PreSET-based cross-point (CP) MRAM to improve programing speed, write energy dissipation and storage density compared to conventional MRAM. Circuit simulation results demonstrate that our PreSET-based CP MRAM can achieve around 67.14% average write energy reduction and 50.86% improvement in programming speed, compared with CP STT-MRAM.

차세대 메모리 소자 중 MRAM(Magnetic Random Access Memory)은 자기저항효과를 이용한 비휘발성 메모리로 기존 메모리를 대체할 것으로 주목을 받고 있다. MRAM은 자기터널 접합 소자를 이용해 구동할 수 있는데, 현재 고집적, 저 전력 소모 등의 장점을 극대화하기 위해 수직자화 특성을 갖는 자기터널 접합 개발과 스핀전달토크를 이용해 구동하는 STT-MRAM(Spin Transfer Torque-MRAM) 개발이 활발히 이루어지고 있다. 따라서 미국, 일본 등 MRAM 강국에서 고집적, 스위칭 전류 감소, 열적 안정성 등의 문제를 해결하기 위한 기술 특허 출원이 증가하고 있으며, 국내의 MRAM 연구기관에서의 특허 출원도 꾸준히 이루어지고 있다. 본고에서는 기존 국내외 특허 출원 및 등록 경향을 분석하고 향후 MRAM 개발방향을 제시하였다. Among the next generation memory, MRAM (Magnetic Random Access Memory) is worthy of notice for substituting the preexisting memory thanks to its non-volatile property and other advantages. Recently perpendicular MRAM and spin transfer torque MRAM techniques are under active investigation to realize a high density and low power consumption. As a result, there are increasing of patents applications for high density, low current density for magnetization switching and high thermal stability. In this paper, we analyze the trend of patent applications and registrations about MRAM and propose a direction of future investigation.

Spin transfer torque (STT) switching is considered as a promising technology to realize Gbit class magnetic random access memories (MRAMs). However, to develop high density MRAM with densities of several Gbit and beyond, there still remains a challenge to reduce critical current density for the STT switching while keeping large thermal stability of the memory layer. One of the solutions for this challenge is thermally assisted MRAM in which the memory layer is heated during the writing. We have studied amorphous GdFeCo and GdFeCo / TbFe exchange coupled bilayer as memory layers of the thermally assisted MRAM cell, and reported the STT switching of these memory layer [1-3]. In this study, we report Gilbert damping constant a and perpendicular anisotropy of GdFeCo / TbFe exchange coupled bilayer, and compare these data with critical current densities Jc. of the STT switching of GdFeCo / TbFe memory layers.

Due to nearly zero leakage power consumption, non-volatile magnetoresistive random access memory (MRAM) is becoming one of the promising candidates for replacing conventional volatile memories (e.g. SRAM and DRAM). In particular, emerging spin-orbit torque (SOT) MRAM is considered to outperform spin-transfer torque (STT) MRAM due to its fast switching, separate read/write paths, and lower energy dissipation. However, the SOT-MRAM technology is still in its infancy; one key design challenge is that the control of SOT-MRAM, which involves three terminals, is more complicated compared with STT-MRAM. In this paper, we propose a novel MRAM write scheme called PRESCOTT1, where the 1 and 0 data values can be written into memory cells through the SOT and STT, respectively. As a result, the write current is unidirectional rather than bi-directional, which addresses the control complexity. Using this unidirectional write scheme, we design a PreSET-based cross-point (CP) MRAM to improve programing speed, write energy dissipation and storage density compared to conventional MRAM. Circuit simulation results demonstrate that our PreSET-based CP MRAM can achieve around 67.14% average write energy reduction and 50.86% improvement in programming speed, compared with CP STT-MRAM.

Magnetic random access memory (MRAM) with its inherent non-volatility is believed to address the large stand-by energy issues in the present memory hierarchy [1]. In recent years, the spin-transfer torque (STT)-MRAM has gradually matured and started to appear in the market. Typically, STT writing of perpendicular magnetic tunnel junction (pMTJ) is limited to a few nanoseconds. This is because STT is collinear and competing with the intrinsic damping of the free-layer (FL), resulting in a long incubation delay [2] and large energy consumption. To mitigate STT limitations, spin-orbit torque (SOT) and voltage control of magnetic anisotropy (VCMA) were proposed as alternative MRAM writing mechanisms. SOT is able to switch the FL of a pMTJ by injecting an in-plane current in an adjacent SOT layer, which enables a three-terminal cell structure with energy-efficient and reliable sub-ns writing capabilities [3]. On the other hand, VCMA promises significant advances toward low-power MRAM. The electronic-based VCMA effect can instantly modify the perpendicular magnetic anisotropy (PMA) of the FL to induce precessional switching at GHz rates and ultra-low energy consumption (fJ) [4]. However, both mechanisms also present technological challenges. The challenges for SOT are currently related to the density and write efficiency: the 2-transistor 1-MTJ cell structure limits the array density, and the SOT write current remains larger than for STT-MRAM, which imposes a large selector transistor to accommodate its write current. For VCMA, the write margin is small, and is subject to the variations in VCMA coefficient and field amplitudes, making write control difficult in dense arrays. Further, a large VCMA effect (>1000fJ/Vm) is mandatory to avoid compromising retention in sub-30nm pMTJ, which remains as a major challenge as typical values in pMTJs are 30-60 fJ/Vm at device level [5]. To overcome the above-cited limitations and to combine the best of these two approaches, voltage-gate assisted spin-orbit torque (VGSOT)-MRAM concept [Fig. 1(a)] has been proposed [6]. In this work, we report on VGSOT switching properties in pMTJ, integrated with our 300mm SOT-MRAM platform [3]. The stack is composed of W(3.5nm)/CoFeB(1nm)/MgO(1.7nm, RA ~ 5kΩ.μm2)/RL/SAF, where the thick MgO ensures pure VCMA gate control without STT contribution. We use an electrical scheme that allows for individual control over SOT/gate pulse amplitudes (VSOT/Vg), and variable pulse duration (tp). Fig. 1(b) shows exemplary SOT switching probability (Psw) curves under different Vg, at tp = 0.4ns. We observe a clear decrease (increase) in VSOT under Vg of 1V (-1V) for both AP-P and P-AP transitions. The critical switching voltage, defined at Psw = 50%, is converted into the critical switching current (Ic) and plotted as a function of 1/tp in Fig. 1(c). It shows a typical linear scaling, i.e. Ic = Ic0 + q/tp in the sub-ns regime for all gate values [7], where Ic0 is the intrinsic critical current and q indicates the nucleation energy for magnetization reversal. The linear dependences of Ic0 and q on Vg [Fig. 1(d)] reflect the direct modification of PMA upon Vg applications and the change of nucleation energy, respectively. We report here a 25% reduction in Ic under Vg = 1V, which corresponds to a 45% reduction in total switching energy to 30fJ at 0.4ns. We further demonstrate that VGSOT offers reliable sub-ns switching with a low write error rate (<10-5) and that VGOST-pMTJ is highly durable against large read/write stresses (>1012) Finally, we benchmark the VGSOT performance at the 5nm technology node against other embedded memory technologies to highlight the VGSOT benefits. It reveals that VGSOT-4MTJ design can reduce the effective cell area to <0.5x of the high-density SRAM at minimal performance degradation. Meanwhile, the constrain of achieving challenging material parameters for VCMA-MTJ (ξ > 1000fJ/Vm) and SOT-MTJ (θSH > 1.5) can be relaxed to reasonable values: ξ = 300fJ/Vm and θSH = 0.45. Our study shows the great potential of this VGSOT approach for fast, dense and low power embedded memory applications. **

With integration density on-chip rocketing up, leakage power dominates the whole power budget of contemporary CMOS based memory, especially for SRAM based on-chip cache. A few non-volatile technologies especially magnetic random access memory (MRAM) technologies are proposed to deal with this issue. Among them, spin transfer torque (STT) MRAM is a possible candidate for future on-chip cache design. However, as the cache capacity keeps growing, STT-MRAM suffers the bottlenecks on both operation speed and power efficiency. In this context, a new NAND-like spin orbit torque (SOT)-based MRAM, NAND-SPIN, which combines the high density of the STT-MRAM and the high performance of the SOT- MRAM has been proposed. Thanks to these benefits, NAND-SPIN could be more suitable for the future large capacity application. In the paper, we evaluate the NAND-SPIN for on-chip cache design in terms of performance, area and power consumption. The runtime system level experimental results show that NAND- SPIN has higher performance/power efficiency compared to SRAM, STT-MRAM and SOT-MRAM, especially in the large capacity situation.

Spin Transfer Torque (STT) Magnetic Random Access Memory (MRAM) is a promising candidate for future on-chip memory, owing to its attractive features like non-volatility, high-density, and zero-leakage [1, 2]. However, the speed and reliability of the standard MRAM cell (1Transistor-1Resistor or 1T-1R cell shown in Fig. 1), are mainly limited by dielectric breakdown of the magnetic tunnel junction (MTJ) [1] under high write-current injection [3, 8] (Fig. 2). In recent years, several device solutions have been proposed that can mitigate this bottleneck by employing separate read and write paths, thereby avoiding write-current injection into the tunneling oxide. Nonlocal-STT [4], Spin-Hall Effect [5], and domain-wall-shift (DWS) [6-8] are three such write mechanisms. We have observed that DWS can be highly energy-efficient and robust, owing to low-voltage, low-current magnetization switching and high cell TMR (tunnel magneto-resistance ratio [1]) [4-6]. However, such bit-cells, with isolated read and write ports, are bound to use two access transistors (Fig. 3), resulting in significant area-penalty. In this work, we propose a multi-level MRAM (ML-MRAM) bit-cell based on DWS that can store 2-bits of data per-cell and can therefore achieve a factor of ~2x reduction in area, read latency as well as read energy (which dominates the total energy consumption) as compared to a DWS-based single-bit-cell. The proposed bit-cell can outperform the standard 1T-1R MRAM (Fig. 1), by a factor of ~2x in terms of area, read-latency, read-energy and by 8x and 4x in terms of write-energy and read disturb margin respectively, apart from mitigating the reliability issues related to dielectric-breakdown. Due to the possibility of sub-nano-second read/write operations, the proposed multi-level bit-cell can be suitable for all levels of the cache hierarchy, including L1 caches (in contrast, previous MRAM proposals have focused on the lower-level caches, which have less stringent speed requirements).

The spin transfer torque (STT) based magnetic random access memory (MRAM) device has been seen as the next general storage device which can realize non-volatile storage and in-memory computing. However, the shape defect that comes from the fabrication process will influence the performance of the MRAM device. In this work, the relationship between the critical current and switching time and the interface edge defect in a CoFeB MRAM is studied by the atomistic spin model. The atomistic simulations that the effect of the interface edge defect depends on the thickness of the magnetic layer, the operating temperature and the driven current density. Our finding should also benefit the control of the fabrication process of the STT-based technologies.

Random Access Memories: Magnetic

Magnetic random-access memory (MRAM) is poised to replace traditional computer memory based on complementary metal-oxide semiconductors (CMOS). MRAM will surpass all other types of memory devices in terms of nonvolatility, low energy dissipation, fast switching speed, radiation hardness, and durability. Although toggle-MRAM is currently a commercial product, it is clear that future developments in MRAM will be based on spin-transfer torque, which makes use of electrons’ spin angular momentum instead of their charge. MRAM will require an amalgamation of magnetics and microelectronics technologies. However, researchers and developers in magnetics and in microelectronics attend different technical conferences, publish in different journals, use different tools, and have different backgrounds in condensed-matter physics, electrical engineering, and materials science. This book is an introduction to MRAM for microelectronics engineers written by specialists in magnetic mat rials and devices. It presents the basic phenomena involved in MRAM, the materials and film stacks being used, the basic principles of the various types of MRAM (toggle and spin-transfer torque; magnetized in-plane or perpendicular-to-plane), the back-end magnetic technology, and recent developments toward logic-in-memory architectures. It helps bridge the cultural gap between the microelectronics and magnetics communities.

20世纪80年代末期自旋电子学研究的兴起开启了现代磁存储技术发展的新纪元.1988年, 巨磁电阻 (giant magnetoresistance, GMR) 效 应 被 发 现 [2,3] .以 GMR磁电阻元件作为磁存储单元, 形成了早期GMR 效应随机存取存储器的研发.1995年, 隧道磁电阻 (tunneling magnetoresistance, TMR)效应 [4,5] 的发现掀 起了磁性隧道结(MTJ)器件的研发热潮.