Spiking Neural Network Implementation on FPGA for Multiclass Classification

Abstract

Spiking Neural Network (SNN) is a particular Artificial Neural Networks (ANN) form. An SNN has similar features as an ANN, but an SNN has a different information system that will allow SNN to have higher energy efficiency than an ANN. This paper presents the design and implementation of an SNN on FPGA. The model of the SNN is designed to be lower power consumption than existing SNN models in the aspect of FPGA implementation and lower accuracy loss than the existing training method in the part of the algorithm. The coding scheme of the SNN model proposed in this paper is the rate coding scheme. This paper introduces a conversion method to directly map the trained parameters from ANN to SNN with negligible classification accuracy loss. Also, this paper demonstrates the technique of FPGA implementation for Spiking Exponential Function, Spiking SoftMax Function and Dynamic Adder Tree. This paper also presents the Time Division Component Reuse technic for lower resource utilization in the FPGA implementation of SNN. The proposed model has a power efficiency of 8841.7 frames per watt with negligible accuracy loss. The benchmark SNN model has a power efficiency of 337.6 frames per watt with an accuracy loss of 1.42 percent. The reference accuracy of the ANN model is 90.36 percent. For comparison, the specific model of the SNN has an accuracy of 90.39 percent.