Abstract
Multipliers play a vital role in DSP applications. The present development in processor design aims at a high-speed multiplier circuit. Generally, the computational power of any system is affected by its multiplier performance in terms of processing speed. The paper describes the parametrical comparison between different multipliers such as booth multiplier, Wallace multiplier, Wallace using compressor technique and modified booth multiplier in terms of processing speed. The delay of the critical path in Wallace multiplier using the compressor technique is minimized. The circuit is synthesized, and high speed is achieved by reducing the delay of the multiplier circuit. Optimizing the speed of the multiplier is the major design issue. However, improving the speed of multiplier may result in a larger area of the circuit.
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