Abstract
We present a method for analyzing several common cell failures in SRAM's, i.e., failures caused by defects produced during VLSI processing. Faults, in 64 k-bit CMOS SRAM's with six-transistor type cells used in this study, are classified in terms of the number of faulty cells. Single-cell and adjacent cell faults, which are dominant, are due to blocked contact holes, aluminum 1 short-circuit defects and blocked via holes. A vector plot showing the relation between single-cell and adjacent-cell failure probabilities suggests that blocked contact holes, aluminum 1 short-circuit defects, and blocked via holes can be isolated. This vector representation is useful in monitoring and improving fabrication yields of VLSI circuits. Vector representations are also given for three and four-cell failure probabilities. >
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