Abstract

Solar-hydrogen energy systems for spacecraft reliably provide energy for carrying out various kinds of unscheduled work on board and for eliminating emergency situations. Surplus energy is constantly accumulated on board in the form of the chemical energy of cryogenic hydrogen.The solar-hydrogen spacecraft power supply system is based on the principle of partial conversion of excess energy generated on board into gaseous and cryogenic hydrogen.The efficiency of converting sunlight into hydrogen is 14%. Solar-hydrogen energy systems are also called rechargeable hydrogen cells. They consist of solar panels that generate electricity, water tanks and a membrane that separates hydrogen and oxygen. The power supply system implements three modes in its operation. Mode A - the planned amount of electrical energy generated by solar cells is consumed to meet the needs of the spacecraft in the normal mode. Mode B - from the excess electricity in excess of the energy consumption on board, the solar panels generate electricity, with the help of which water is electrolyzed. The resulting hydrogen is stored in special tanks and can be used during the peak period of energy consumption. Mode C - part of the hydrogen can be liquefied by the onboard cryogenerator and it can be used to generate electricity in fuel cells in super-peak power consumption situations: accidents, repairs, experiments that require a lot of energy. The efficiency of converting sunlight into cryogenic hydrogen is 5%.The article considers a new version of the median signal selection element, which provides the possibility of practically unlimited scaling of the number of input signals without loss of performance, as well as the ability to monitor malfunctions or failures in the operation of the selection element itself.The experiments have shown that the implementation of a selection element for 7 inputs takes no more than 432 logical cells on the Altera Cyclone IV EP4CE115F29C7 FPGA, which is much less than the amount occupied by the analogs discussed in the article. In this case, the delay in calculating the median signal does not exceed one FPGA cycle.

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